changeset 40526b73c7db in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=40526b73c7db
description:
stats: Bump stats after Minor switcheroo inclusion
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
| 1223 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
| 115 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
| 11 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 4500 ++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
| 1223 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
| 2296 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
| 11 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
| 4996 +++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
| Bin
9 files changed, 8163 insertions(+), 6212 deletions(-)
diffs (truncated from 15456 to 300 lines):
diff -r 6d86c48f7806 -r 40526b73c7db
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
---
a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
Thu Jul 30 10:16:28 2015 +0100
+++
b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
Thu Jul 30 10:16:36 2015 +0100
@@ -10,27 +10,25 @@
[system]
type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler
intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
voltage_domain
+children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler
intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
voltage_domain
atags_addr=134217728
-boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
+boot_loader=/work/gem5/dist/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480
norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
flags_addr=469827632
gic_cpu_addr=738205696
-have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -44,7 +42,7 @@
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_3/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -87,7 +85,7 @@
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
+image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -475,92 +473,67 @@
eventq_index=0
[system.cpu2]
-type=DerivO3CPU
-children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
+type=MinorCPU
+children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer
branchPred=system.cpu2.branchPred
-cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeCycleInput=true
+decodeInputBufferSize=3
+decodeInputWidth=2
+decodeToExecuteForwardDelay=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu2.dstage2_mmu
dtb=system.cpu2.dtb
+enableIdling=true
eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu2.fuPool
+executeAllowEarlyMemoryIssue=true
+executeBranchDelay=1
+executeCommitLimit=2
+executeCycleInput=true
+executeFuncUnits=system.cpu2.executeFuncUnits
+executeInputBufferSize=7
+executeInputWidth=2
+executeIssueLimit=2
+executeLSQMaxStoreBufferStoresPerCycle=2
+executeLSQRequestsQueueSize=1
+executeLSQStoreBufferSize=5
+executeLSQTransfersQueueSize=2
+executeMaxAccessesInMemory=2
+executeMemoryCommitLimit=1
+executeMemoryIssueLimit=1
+executeMemoryWidth=0
+executeSetTraceTimeOnCommit=true
+executeSetTraceTimeOnIssue=false
+fetch1FetchLimit=1
+fetch1LineSnapWidth=0
+fetch1LineWidth=0
+fetch1ToFetch2BackwardDelay=1
+fetch1ToFetch2ForwardDelay=1
+fetch2CycleInput=true
+fetch2InputBufferSize=2
+fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
interrupts=Null
isa=system.cpu2.isa
-issueToExecuteDelay=1
-issueWidth=8
istage2_mmu=system.cpu2.istage2_mmu
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
numThreads=1
profile=0
progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
socket_id=0
-squashWidth=8
-store_set_clear_period=250000
switched_out=true
system=system
tracer=system.cpu2.tracer
-trapLatency=13
-wbWidth=8
workload=
[system.cpu2.branchPred]
@@ -619,312 +592,388 @@
num_squash_per_cycle=2
sys=system
-[system.cpu2.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList8
-FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1
system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3
system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5
system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+[system.cpu2.executeFuncUnits]
+type=MinorFUPool
+children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5
funcUnits6
eventq_index=0
+funcUnits=system.cpu2.executeFuncUnits.funcUnits0
system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2
system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4
system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6
-[system.cpu2.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
+[system.cpu2.executeFuncUnits.funcUnits0]
+type=MinorFU
+children=opClasses timings
+cantForwardFromFUIndices=
eventq_index=0
-opList=system.cpu2.fuPool.FUList0.opList
+issueLat=1
+opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses
+opLat=3
+timings=system.cpu2.executeFuncUnits.funcUnits0.timings
-[system.cpu2.fuPool.FUList0.opList]
-type=OpDesc
+[system.cpu2.executeFuncUnits.funcUnits0.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses
+
+[system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses]
+type=MinorOpClass
eventq_index=0
opClass=IntAlu
-opLat=1
-pipelined=true
-[system.cpu2.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
+[system.cpu2.executeFuncUnits.funcUnits0.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
eventq_index=0
-opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
-[system.cpu2.fuPool.FUList1.opList0]
-type=OpDesc
+[system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu2.executeFuncUnits.funcUnits1]
+type=MinorFU
+children=opClasses timings
+cantForwardFromFUIndices=
+eventq_index=0
+issueLat=1
+opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses
+opLat=3
+timings=system.cpu2.executeFuncUnits.funcUnits1.timings
+
+[system.cpu2.executeFuncUnits.funcUnits1.opClasses]
+type=MinorOpClassSet
+children=opClasses
+eventq_index=0
+opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses
+
+[system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses]
+type=MinorOpClass
+eventq_index=0
+opClass=IntAlu
+
+[system.cpu2.executeFuncUnits.funcUnits1.timings]
+type=MinorFUTiming
+children=opClasses
+description=Int
+eventq_index=0
+extraAssumedLat=0
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses
+srcRegsRelativeLats=2
+suppress=false
+
+[system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu2.executeFuncUnits.funcUnits2]
+type=MinorFU
+children=opClasses timings
+cantForwardFromFUIndices=
+eventq_index=0
+issueLat=1
+opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses
+opLat=3
+timings=system.cpu2.executeFuncUnits.funcUnits2.timings
+
+[system.cpu2.executeFuncUnits.funcUnits2.opClasses]
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