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Review request for Default. Repository: gem5 Description ------- Changeset 11017:b37918d5063f --------------------------- ruby: slicc: fix naming of variables The way SLICC compiler has been written, it was difficult to use a variable that appears in the base class AbstractController without adding some special code to the file src/mem/slicc/ast/ObjDeclAST.py. This eliminates the need for any such special code. The problem ultimately turned out to be the way SLICC handles pointer and non-pointer variables. Till now, SLICC tried to handle everything using pointers, unless some special rules were specified, as was being done for three variables: version, machineID and clusterID. Now the Var class will have a field that indicates whether a variable is pointer or not. This field is used to differentiate between pointer variables and other variables. Pointer-based variables are allocated in the init() function of the controller, as was the case before. Other variables now need not be pointer based. Variables that need the constructor be called on them will now necessarily be declared as pointers. The protocols currently in gem5 have been changed accordingly. Diffs ----- src/mem/slicc/ast/InPortDeclAST.py a618349a7953 src/mem/slicc/ast/LocalVariableAST.py a618349a7953 src/mem/protocol/MOESI_CMP_directory-dma.sm a618349a7953 src/mem/protocol/MOESI_CMP_token-L1cache.sm a618349a7953 src/mem/protocol/MOESI_CMP_token-L2cache.sm a618349a7953 src/mem/protocol/MOESI_CMP_token-dir.sm a618349a7953 src/mem/protocol/MOESI_hammer-cache.sm a618349a7953 src/mem/protocol/MOESI_hammer-dir.sm a618349a7953 src/mem/slicc/ast/ActionDeclAST.py a618349a7953 src/mem/slicc/ast/EnqueueStatementAST.py a618349a7953 src/mem/slicc/ast/FormalParamAST.py a618349a7953 src/mem/protocol/MESI_Three_Level-L0cache.sm a618349a7953 src/mem/protocol/MESI_Three_Level-L1cache.sm a618349a7953 src/mem/protocol/MESI_Two_Level-L1cache.sm a618349a7953 src/mem/protocol/MESI_Two_Level-L2cache.sm a618349a7953 src/mem/protocol/MESI_Two_Level-dir.sm a618349a7953 src/mem/protocol/MI_example-cache.sm a618349a7953 src/mem/protocol/MI_example-dir.sm a618349a7953 src/mem/protocol/MOESI_CMP_directory-L1cache.sm a618349a7953 src/mem/protocol/MOESI_CMP_directory-L2cache.sm a618349a7953 src/mem/protocol/MOESI_CMP_directory-dir.sm a618349a7953 src/mem/slicc/ast/ObjDeclAST.py a618349a7953 src/mem/slicc/ast/OutPortDeclAST.py a618349a7953 src/mem/slicc/ast/PeekStatementAST.py a618349a7953 src/mem/slicc/symbols/StateMachine.py a618349a7953 src/mem/slicc/symbols/Type.py a618349a7953 src/mem/slicc/symbols/Var.py a618349a7953 Diff: http://reviews.gem5.org/r/3002/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
