changeset 0ff78be3bc67 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0ff78be3bc67
description:
mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube
(HMC).
SerialLink is a simple variation of the Bridge class, with the ability
to
account for the latency of packet serialization. Also trySendTiming has
been
modified to correctly model bandwidth.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/mem/SConscript | 3 +
src/mem/SerialLink.py | 63 +++++++
src/mem/serial_link.cc | 437 +++++++++++++++++++++++++++++++++++++++++++++++++
src/mem/serial_link.hh | 329 ++++++++++++++++++++++++++++++++++++
4 files changed, 832 insertions(+), 0 deletions(-)
diffs (truncated from 868 to 300 lines):
diff -r 07b0dacf27d6 -r 0ff78be3bc67 src/mem/SConscript
--- a/src/mem/SConscript Tue Nov 03 12:17:56 2015 -0600
+++ b/src/mem/SConscript Tue Nov 03 12:17:57 2015 -0600
@@ -43,6 +43,7 @@
SimObject('SimpleMemory.py')
SimObject('XBar.py')
SimObject('HMCController.py')
+SimObject('SerialLink.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -66,6 +67,7 @@
Source('tport.cc')
Source('xbar.cc')
Source('hmc_controller.cc')
+Source('serial_link.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')
@@ -104,6 +106,7 @@
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
DebugFlag('HMCController')
+DebugFlag('SerialLink')
DebugFlag("MemChecker")
DebugFlag("MemCheckerMonitor")
diff -r 07b0dacf27d6 -r 0ff78be3bc67 src/mem/SerialLink.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/SerialLink.py Tue Nov 03 12:17:57 2015 -0600
@@ -0,0 +1,63 @@
+# Copyright (c) 2012-2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2015 The University of Bologna
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+# Andreas Hansson
+# Erfan Azarkhish
+
+from m5.params import *
+from MemObject import MemObject
+
+# SerialLink is a simple variation of the Bridge class, with the ability to
+# account for the latency of packet serialization.
+
+class SerialLink(MemObject):
+ type = 'SerialLink'
+ cxx_header = "mem/serial_link.hh"
+ slave = SlavePort('Slave port')
+ master = MasterPort('Master port')
+ req_size = Param.Unsigned(16, "The number of requests to buffer")
+ resp_size = Param.Unsigned(16, "The number of responses to buffer")
+ delay = Param.Latency('0ns', "The latency of this serial_link")
+ ranges = VectorParam.AddrRange([AllMemory],
+ "Address ranges to pass through the serial_link")
+ # Bandwidth of the serial link is determined by the clock domain which the
+ # link belongs to and the number of lanes:
+ num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
+ "link. (aka. lane width)")
diff -r 07b0dacf27d6 -r 0ff78be3bc67 src/mem/serial_link.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/serial_link.cc Tue Nov 03 12:17:57 2015 -0600
@@ -0,0 +1,437 @@
+/*
+ * Copyright (c) 2011-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2015 The University of Bologna
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Steve Reinhardt
+ * Andreas Hansson
+ * Erfan Azarkhish
+ */
+
+/**
+ * @file
+ * Implementation of the SerialLink Class, modeling Hybrid-Memory-Cube's
+ * serial interface.
+ */
+
+#include "mem/serial_link.hh"
+
+#include "base/trace.hh"
+#include "debug/SerialLink.hh"
+#include "params/SerialLink.hh"
+
+
+SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
+ SerialLink& _serial_link,
+ SerialLinkMasterPort& _masterPort,
+ Cycles _delay, int _resp_limit,
+ const std::vector<AddrRange>&
+ _ranges)
+ : SlavePort(_name, &_serial_link), serial_link(_serial_link),
+ masterPort(_masterPort), delay(_delay),
+ ranges(_ranges.begin(), _ranges.end()),
+ outstandingResponses(0), retryReq(false),
+ respQueueLimit(_resp_limit), sendEvent(*this)
+{
+}
+
+SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
+ _name, SerialLink& _serial_link,
+ SerialLinkSlavePort& _slavePort,
+ Cycles _delay, int _req_limit)
+ : MasterPort(_name, &_serial_link), serial_link(_serial_link),
+ slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
+ sendEvent(*this)
+{
+}
+
+SerialLink::SerialLink(SerialLinkParams *p)
+ : MemObject(p),
+ slavePort(p->name + ".slave", *this, masterPort,
+ ticksToCycles(p->delay), p->resp_size, p->ranges),
+ masterPort(p->name + ".master", *this, slavePort,
+ ticksToCycles(p->delay), p->req_size),
+ num_lanes(p->num_lanes)
+{
+}
+
+BaseMasterPort&
+SerialLink::getMasterPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "master")
+ return masterPort;
+ else
+ // pass it along to our super class
+ return MemObject::getMasterPort(if_name, idx);
+}
+
+BaseSlavePort&
+SerialLink::getSlavePort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "slave")
+ return slavePort;
+ else
+ // pass it along to our super class
+ return MemObject::getSlavePort(if_name, idx);
+}
+
+void
+SerialLink::init()
+{
+ // make sure both sides are connected and have the same block size
+ if (!slavePort.isConnected() || !masterPort.isConnected())
+ fatal("Both ports of a serial_link must be connected.\n");
+
+ // notify the master side of our address ranges
+ slavePort.sendRangeChange();
+}
+
+bool
+SerialLink::SerialLinkSlavePort::respQueueFull() const
+{
+ return outstandingResponses == respQueueLimit;
+}
+
+bool
+SerialLink::SerialLinkMasterPort::reqQueueFull() const
+{
+ return transmitList.size() == reqQueueLimit;
+}
+
+bool
+SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt)
+{
+ // all checks are done when the request is accepted on the slave
+ // side, so we are guaranteed to have space for the response
+ DPRINTF(SerialLink, "recvTimingResp: %s addr 0x%x\n",
+ pkt->cmdString(), pkt->getAddr());
+
+ DPRINTF(SerialLink, "Request queue size: %d\n", transmitList.size());
+
+ // @todo: We need to pay for this and not just zero it out
+ pkt->headerDelay = pkt->payloadDelay = 0;
+
+ // This is similar to what happens for the request packets:
+ // The serializer will start serialization as soon as it receives the
+ // first flit, but the deserializer (at the host side in this case), will
+ // have to wait to receive the whole packet. So we only account for the
+ // deserialization latency.
+ Cycles cycles = delay;
+ cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes));
+ Tick t = serial_link.clockEdge(cycles);
+
+ //@todo: If the processor sends two uncached requests towards HMC and the
+ // second one is smaller than the first one. It may happen that the second
+ // one crosses this link faster than the first one (because the packet
+ // waits in the link based on its size). This can reorder the received
+ // response.
+ slavePort.schedTimingResp(pkt, t);
+
+ return true;
+}
+
+bool
+SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt)
+{
+ DPRINTF(SerialLink, "recvTimingReq: %s addr 0x%x\n",
+ pkt->cmdString(), pkt->getAddr());
+
+ // we should not see a timing request if we are already in a retry
+ assert(!retryReq);
+
+ DPRINTF(SerialLink, "Response queue size: %d outresp: %d\n",
+ transmitList.size(), outstandingResponses);
+
+ // if the request queue is full then there is no hope
+ if (masterPort.reqQueueFull()) {
+ DPRINTF(SerialLink, "Request queue full\n");
+ retryReq = true;
+ } else if ( !retryReq ) {
+ // look at the response queue if we expect to see a response
+ bool expects_response = pkt->needsResponse() &&
+ !pkt->memInhibitAsserted();
+ if (expects_response) {
+ if (respQueueFull()) {
+ DPRINTF(SerialLink, "Response queue full\n");
+ retryReq = true;
+ } else {
+ // ok to send the request with space for the response
+ DPRINTF(SerialLink, "Reserving space for response\n");
+ assert(outstandingResponses != respQueueLimit);
+ ++outstandingResponses;
+
+ // no need to set retryReq to false as this is already the
+ // case
+ }
+ }
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