> On Nov. 5, 2015, 1:20 a.m., Steve Reinhardt wrote: > > src/mem/cache/base.hh, line 244 > > <http://reviews.gem5.org/r/3156/diff/3/?file=51385#file51385line244> > > > > so I assume this is just to give us a definition on BaseCache that we > > can use above? Is there any good reason we still have the BaseCache/Cache > > split now that the templating is gone? > > > > Alternatively, we could move allocateMissBuffer(), > > allocateWriteBuffer(), and this function down into Cache. The only reason > > they were up here in the first place was to factor out some common > > non-templated code, but now there's really no reason for them to be up in > > BaseCache at all IMO.
It is indeed needed so that we can use it in the call to allocate buffers in BaseCache. I am on the fence with regards to the class hierarchy, and in any case it should not be changed in this patch. Going forward I think there is a good reason to keep the BaseCache and Cache split, but move things around a bit. For a non-coherent system cache (after the point of coherency), we may still want to use the cache block and tags, prefetcher classes etc, so having these tied to the BaseCache makes sense. Exactly what goes into BaseCache, and what goes into Cache and NonCoherentCache is definitely up for discussion. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3156/#review7483 ----------------------------------------------------------- On Nov. 4, 2015, 12:52 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3156/ > ----------------------------------------------------------- > > (Updated Nov. 4, 2015, 12:52 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11195:8bf51d20200d > --------------------------- > mem: Add cache clusivity > > This patch adds a parameter to control the cache clusivity, that is if > the cache is mostly inclusive or exclusive. At the moment there is no > intention to support strict policies, and thus the options are: 1) > mostly inclusive, or 2) mostly exclusive. > > The choice of policy guides the behaviuor on a cache fill, and a new > helper function, allocOnFill, is created to encapsulate the decision > making process. For the timing mode, the decision is annotated on the > MSHR on sending out the downstream packet, and in atomic we directly > pass the decision to handleFill. We (ab)use the tempBlock in cases > where we are not allocating on fill, leaving the rest of the cache > unaffected. Simple and effective. > > This patch also makes it more explicit that multiple caches are > allowed to consider a block writable (this is the case > also before this patch). That is, for a mostly inclusive cache, > multiple caches upstream may also consider the block exclusive. The > caches considering the block writable/exclusive all appear along the > same path to memory, and from a coherency protocol point of view it > works due to the fact that we always snoop upwards in zero time before > querying any downstream cache. > > Note that this patch does not introduce clean writebacks. Thus, for > clean lines we are essentially removing a cache level if it is made > mostly exclusive. For example, lines from the read-only L1 instruction > cache or table-walker cache are always clean, and simply get dropped > rather than being passed to the L2. If the L2 is mostly exclusive and > does not allocate on fill it will thus never hold the line. A follow > on patch adds the clean writebacks. > > The patch changes the L2 of the O3_ARM_v7a CPU configuration to be > mostly exclusive (and stats are affected accordingly). > > > Diffs > ----- > > configs/common/O3_ARM_v7a.py 2d1d51615e0e > src/mem/cache/Cache.py 2d1d51615e0e > src/mem/cache/base.hh 2d1d51615e0e > src/mem/cache/cache.hh 2d1d51615e0e > src/mem/cache/cache.cc 2d1d51615e0e > src/mem/cache/mshr.hh 2d1d51615e0e > src/mem/cache/mshr.cc 2d1d51615e0e > src/mem/cache/mshr_queue.hh 2d1d51615e0e > src/mem/cache/mshr_queue.cc 2d1d51615e0e > > Diff: http://reviews.gem5.org/r/3156/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
