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Ship it! If you come up with better names, that's great, but even if not this looks good to me. - Steve Reinhardt On Nov. 5, 2015, 3:02 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3158/ > ----------------------------------------------------------- > > (Updated Nov. 5, 2015, 3:02 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11198:d5dd32064cc2 > --------------------------- > mem: Add an option to perform clean writebacks from caches > > This patch adds the necessary commands and cache functionality to > allow clean writebacks. This functionality is crucial, especially when > having exclusive (victim) caches. For example, if read-only L1 > instruction caches are not sending clean writebacks, there will never > be any spills from the L1 to the L2. At the moment the cache model > defaults to not sending clean writebacks, and this should possibly be > re-evaluated. > > The implementation of clean writebacks relies on a new packet command > WritebackClean, which acts much like a Writeback (renamed > WritebackDirty), and also much like a CleanEvict. On eviction of a > clean block the cache either sends a clean evict, or a clean > writeback, and if any copies are still cached upstream the clean > evict/writeback is dropped. Similarly, if a clean evict/writeback > reaches a cache where there are outstanding MSHRs for the block, the > packet is dropped. In the typical case though, the clean writeback > allocates a block in the downstream cache, and marks it writable if > the evicted block was writable. > > The patch changes the O3_ARM_v7a L1 cache configuration and the > default L1 caches in config/common/Caches.py > > > Diffs > ----- > > src/mem/packet.cc 854e61d5390e > src/mem/snoop_filter.cc 854e61d5390e > src/mem/cache/cache.cc 854e61d5390e > src/mem/coherent_xbar.cc 854e61d5390e > src/mem/packet.hh 854e61d5390e > configs/common/Caches.py 854e61d5390e > configs/common/O3_ARM_v7a.py 854e61d5390e > src/mem/abstract_mem.cc 854e61d5390e > src/mem/cache/Cache.py 854e61d5390e > src/mem/cache/base.hh 854e61d5390e > src/mem/cache/cache.hh 854e61d5390e > > Diff: http://reviews.gem5.org/r/3158/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
