changeset 46c7b3e35720 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=46c7b3e35720
description:
arm: Squash after returning from exceptions in v7
Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
diffstat:
src/arch/arm/isa/insts/data.isa | 6 ++++--
src/arch/arm/isa/insts/macromem.isa | 4 ++--
src/arch/arm/isa/insts/misc.isa | 3 ++-
3 files changed, 8 insertions(+), 5 deletions(-)
diffs (52 lines):
diff -r 414abc839464 -r 46c7b3e35720 src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Mon Feb 29 19:13:13 2016 -0600
+++ b/src/arch/arm/isa/insts/data.isa Mon Feb 29 19:13:13 2016 -0600
@@ -273,10 +273,12 @@
'''
buildImmDataInst(mnem + 's', code, flagType,
suffix = "ImmPclr", buildCc = False,
- instFlags =
["IsSerializeAfter","IsNonSpeculative"])
+ instFlags =
["IsSerializeAfter","IsNonSpeculative",
+ "IsSquashAfter"])
buildRegDataInst(mnem + 's', code, flagType,
suffix = "RegPclr", buildCc = False,
- instFlags =
["IsSerializeAfter","IsNonSpeculative"])
+ instFlags =
["IsSerializeAfter","IsNonSpeculative",
+ "IsSquashAfter"])
buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
diff -r 414abc839464 -r 46c7b3e35720 src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Mon Feb 29 19:13:13 2016 -0600
+++ b/src/arch/arm/isa/insts/macromem.isa Mon Feb 29 19:13:13 2016 -0600
@@ -124,7 +124,7 @@
'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest},
['IsMicroop','IsNonSpeculative',
- 'IsSerializeAfter'])
+ 'IsSerializeAfter', 'IsSquashAfter'])
microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
@@ -668,7 +668,7 @@
{'code': microRetUopCode % 'URb',
'predicate_test': predicateTest},
['IsMicroop', 'IsNonSpeculative',
- 'IsSerializeAfter'])
+ 'IsSerializeAfter', 'IsSquashAfter'])
setPCCPSRDecl = '''
CPSR cpsrOrCondCodes = URc;
diff -r 414abc839464 -r 46c7b3e35720 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Mon Feb 29 19:13:13 2016 -0600
+++ b/src/arch/arm/isa/insts/misc.isa Mon Feb 29 19:13:13 2016 -0600
@@ -130,7 +130,8 @@
eretIop = InstObjParams("eret", "Eret", "PredOp",
{ "code": eretCode,
"predicate_test": predicateTest },
- ["IsNonSpeculative", "IsSerializeAfter"])
+ ["IsNonSpeculative", "IsSerializeAfter",
+ "IsSquashAfter"])
header_output += BasicDeclare.subst(eretIop)
decoder_output += BasicConstructor.subst(eretIop)
exec_output += PredOpExecute.subst(eretIop)
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