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I think this is a good idea, but... The main reason we haven't enabled this by default is because of the way it interacts with interrupts. Due to the the fact that the PMU has interrupts, we should ideally add it via the platform since that's were the interrupt map is defined. To make matters even more compicated, the current implementation, like many real implementations, uses SPIs. This works fine in single-core configurations (or configurations with a handfull of cores), but isn't very flexible since each core needs its own interrupt. At least Linux supports PMUs with PPIs, so I'm tempted to say that a PPI would make most sense since that'd allow us to define a single interrupt and forget about it. I won't have time to add PPI support myself anytime soon, but I'm happy to give you a hand if you want to give it a stab. You know where to find me. :) configs/common/Options.py (lines 336 - 338) <http://reviews.gem5.org/r/3377/#comment6977> Add this together with the other ARM-specific options instead. See for example --machine-type above. src/arch/arm/ArmISA.py (line 55) <http://reviews.gem5.org/r/3377/#comment6978> This is a bit scary since the PMU is needs to know which interrupt to use and that's generally defined by the platform code (see src/dev/arm/ReaView.py). Ideally, this device should live with the other platform devices, but I'm not sure how we would wire it to the ISA in that case. - Andreas Sandberg On March 15, 2016, 5 p.m., Bjoern A. Zeeb wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3377/ > ----------------------------------------------------------- > > (Updated March 15, 2016, 5 p.m.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > arm,dev,config: always preent the PMU but add option to enable > > Always attach the PMU to an ARM core but do not enable the > relevant instructions/events unless asked for by setting the > new command line option --pmu. > > Note: this should work fine for 1 core systems, for multi-core > there might be an interrupt delivery issue still (SPI vs. PPI). > Consider this as an example for people who want to work on it > as the question has previously come up on the mailing lists on > how to hook this up. > > > Diffs > ----- > > configs/common/Options.py 2fd64ea0a7cb > configs/example/fs.py 2fd64ea0a7cb > src/arch/arm/ArmISA.py 2fd64ea0a7cb > > Diff: http://reviews.gem5.org/r/3377/diff/ > > > Testing > ------- > > > Thanks, > > Bjoern A. Zeeb > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
