----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3449/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Add support for McVerSi memory consistency verification framework This patch implements the Gem5-specific portion of McVerSi (a framework for simulation-based memory consistency verification) [1]. Currently, only the O3CPU is supported. [1] http://ac.marcoelver.com/research/mcversi Diffs ----- src/arch/arm/isa/formats/aarch64.isa 48b1f224eddc src/arch/arm/isa/formats/m5ops.isa 48b1f224eddc src/arch/arm/isa/insts/m5ops.isa 48b1f224eddc src/cpu/o3/commit_impl.hh 48b1f224eddc src/cpu/o3/dyn_inst.hh 48b1f224eddc src/cpu/o3/dyn_inst_impl.hh 48b1f224eddc src/cpu/o3/lsq_unit_impl.hh 48b1f224eddc src/sim/SConscript 48b1f224eddc src/sim/mcversi.hh PRE-CREATION src/sim/mcversi.cc PRE-CREATION src/sim/pseudo_inst.hh 48b1f224eddc src/sim/pseudo_inst.cc 48b1f224eddc util/m5/m5op.h 48b1f224eddc util/m5/m5op_x86.S 48b1f224eddc util/m5/m5ops.h 48b1f224eddc Diff: http://reviews.gem5.org/r/3449/diff/ Testing ------- Unless explicitly enabled (via loading appropriate workload), this is component is unused. However, bugs have been found elsewhere in Gem5 by McVerSi (which is its purpose!). (I will not restate them here to keep the discussion on topic.) Thanks, Marco Elver _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
