At this point I don't find it that much of a burden. It would be great if anyone that's using it would speak up, so we know not to kill it next time the question comes up, but I don't see a need to think about it unless/until some issue arises that requires more than me re-running the stats every once in a while.
Steve On Sun, May 8, 2016 at 11:22 AM Andreas Hansson <[email protected]> wrote: > Hi Steve, > > Should we perhaps just retire EIO? > > Andreas > > On 07/05/2016, 19:43, "gem5-dev on behalf of Steve Reinhardt" > <[email protected] on behalf of [email protected]> wrote: > > >changeset a22c4bac7e15 in /z/repo/gem5 > >details: http://repo.gem5.org/gem5?cmd=changeset;node=a22c4bac7e15 > >description: > >tests: update EIO ref stats for removed cache stats > > > >Complaints about changes in EIO tests were due to reference files > >that still have removed cache stats from cset 11454:e55afadc4e19. > > > >diffstat: > > > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini | > >3 + > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json | > >5 +- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout | > >6 +- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | > >10 +- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini | > >7 +- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json | > >15 ++- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout | > >6 +- > > tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | > >19 +--- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini | > >13 +-- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json | > >33 +++----- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | > >6 +- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | > >6 +- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | > >37 +-------- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | > >13 +-- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json | > >33 +++----- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr | > >4 +- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | > >6 +- > > tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | > >37 +-------- > > 18 files changed, 93 insertions(+), 166 deletions(-) > > > >diffs (truncated from 1173 to 300 lines): > > > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.iniFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.iniSat > >May 07 14:43:06 2016 -0400 > >@@ -29,6 +29,8 @@ > > num_work_ids=16 > > readfile= > > symbolfile= > >+thermal_components= > >+thermal_model=Null > > work_begin_ckpt_count=0 > > work_begin_cpu_id_exit=-1 > > work_begin_exit_count=0 > >@@ -141,6 +143,7 @@ > > eventq_index=0 > > forward_latency=4 > > frontend_latency=3 > >+point_of_coherency=true > > response_latency=2 > > snoop_filter=Null > > snoop_response_latency=4 > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.jsonFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.jsonSat > >May 07 14:43:06 2016 -0400 > >@@ -15,6 +15,7 @@ > > "role": "SLAVE" > > }, > > "name": "membus", > >+ "point_of_coherency": true, > > "snoop_filter": null, > > "forward_latency": 4, > > "clk_domain": "system.clk_domain", > >@@ -37,8 +38,10 @@ > > }, > > "symbolfile": "", > > "readfile": "", > >+ "thermal_model": null, > > "cxx_class": "System", > > "load_offset": 0, > >+ "work_begin_exit_count": 0, > > "work_end_ckpt_count": 0, > > "memories": [ > > "system.physmem" > >@@ -105,7 +108,7 @@ > > "in_addr_map": true > > }, > > "work_cpus_ckpt_count": 0, > >- "work_begin_exit_count": 0, > >+ "thermal_components": [], > > "path": "system", > > "cpu_clk_domain": { > > "name": "cpu_clk_domain", > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout > >--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simoutFri > >May 06 17:00:54 2016 -0400 > >+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simoutSat > >May 07 14:43:06 2016 -0400 > >@@ -1,9 +1,9 @@ > > gem5 Simulator System. http://gem5.org > > gem5 is copyrighted software; use the --copyright option for details. > > > >-gem5 compiled Feb 1 2016 02:06:47 > >-gem5 started Feb 1 2016 02:07:02 > >-gem5 executing on zizzer, pid 44725 > >+gem5 compiled May 7 2016 13:41:33 > >+gem5 started May 7 2016 13:42:02 > >+gem5 executing on zizzer, pid 51296 > > command line: build/ALPHA/gem5.opt -d > >build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re > >/z/stever/hg/gem5/tests/run.py > >build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic > > > > Global frequency set at 1000000000000 ticks per second > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txtFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txtSat > >May 07 14:43:06 2016 -0400 > >@@ -4,11 +4,11 @@ > > sim_ticks 250015500 > > # Number of ticks simulated > > final_tick 250015500 > > # Number of ticks from beginning of simulation (restored from > >checkpoints and never reset) > > sim_freq 1000000000000 > > # Frequency of simulated ticks > >-host_inst_rate 1689656 > > # Simulator instruction rate (inst/s) > >-host_op_rate 1689524 > > # Simulator op (including micro ops) rate (op/s) > >-host_tick_rate 844754706 > > # Simulator tick rate (ticks/s) > >-host_mem_usage 219516 > > # Number of bytes of host memory used > >-host_seconds 0.30 > > # Real time elapsed on the host > >+host_inst_rate 1181428 > > # Simulator instruction rate (inst/s) > >+host_op_rate 1181354 > > # Simulator op (including micro ops) rate (op/s) > >+host_tick_rate 590676886 > > # Simulator tick rate (ticks/s) > >+host_mem_usage 220296 > > # Number of bytes of host memory used > >+host_seconds 0.42 > > # Real time elapsed on the host > > sim_insts 500001 > > # Number of instructions simulated > > sim_ops 500001 > > # Number of ops (including micro ops) simulated > > system.voltage_domain.voltage 1 > > # Voltage in Volts > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.iniFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.iniSat > >May 07 14:43:06 2016 -0400 > >@@ -29,6 +29,8 @@ > > num_work_ids=16 > > readfile= > > symbolfile= > >+thermal_components= > >+thermal_model=Null > > work_begin_ckpt_count=0 > > work_begin_cpu_id_exit=-1 > > work_begin_exit_count=0 > >@@ -88,7 +90,6 @@ > > clusivity=mostly_incl > > demand_mshr_reserve=1 > > eventq_index=0 > >-forward_snoops=true > > hit_latency=2 > > is_read_only=false > > max_miss_count=0 > >@@ -130,7 +131,6 @@ > > clusivity=mostly_incl > > demand_mshr_reserve=1 > > eventq_index=0 > >-forward_snoops=true > > hit_latency=2 > > is_read_only=true > > max_miss_count=0 > >@@ -181,7 +181,6 @@ > > clusivity=mostly_incl > > demand_mshr_reserve=1 > > eventq_index=0 > >-forward_snoops=true > > hit_latency=20 > > is_read_only=false > > max_miss_count=0 > >@@ -216,6 +215,7 @@ > > eventq_index=0 > > forward_latency=0 > > frontend_latency=1 > >+point_of_coherency=false > > response_latency=1 > > snoop_filter=system.cpu.toL2Bus.snoop_filter > > snoop_response_latency=1 > >@@ -271,6 +271,7 @@ > > eventq_index=0 > > forward_latency=4 > > frontend_latency=3 > >+point_of_coherency=true > > response_latency=2 > > snoop_filter=Null > > snoop_response_latency=4 > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.jsonFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.jsonSat > >May 07 14:43:06 2016 -0400 > >@@ -14,6 +14,7 @@ > > "role": "SLAVE" > > }, > > "name": "membus", > >+ "point_of_coherency": true, > > "snoop_filter": null, > > "forward_latency": 4, > > "clk_domain": "system.clk_domain", > >@@ -36,8 +37,10 @@ > > }, > > "symbolfile": "", > > "readfile": "", > >+ "thermal_model": null, > > "cxx_class": "System", > > "load_offset": 0, > >+ "work_begin_exit_count": 0, > > "work_end_ckpt_count": 0, > > "memories": [ > > "system.physmem" > >@@ -104,7 +107,7 @@ > > "in_addr_map": true > > }, > > "work_cpus_ckpt_count": 0, > >- "work_begin_exit_count": 0, > >+ "thermal_components": [], > > "path": "system", > > "cpu_clk_domain": { > > "name": "cpu_clk_domain", > >@@ -158,6 +161,7 @@ > > "role": "SLAVE" > > }, > > "name": "toL2Bus", > >+ "point_of_coherency": false, > > "snoop_filter": { > > "name": "snoop_filter", > > "system": "system", > >@@ -227,11 +231,10 @@ > > "role": "MASTER" > > }, > > "type": "Cache", > >- "forward_snoops": true, > > "writeback_clean": true, > > "hit_latency": 2, > >+ "demand_mshr_reserve": 1, > > "tgts_per_mshr": 20, > >- "demand_mshr_reserve": 1, > > "addr_ranges": [ > > "0:18446744073709551615" > > ], > >@@ -291,11 +294,10 @@ > > "role": "MASTER" > > }, > > "type": "Cache", > >- "forward_snoops": true, > > "writeback_clean": false, > > "hit_latency": 20, > >+ "demand_mshr_reserve": 1, > > "tgts_per_mshr": 12, > >- "demand_mshr_reserve": 1, > > "addr_ranges": [ > > "0:18446744073709551615" > > ], > >@@ -374,11 +376,10 @@ > > "role": "MASTER" > > }, > > "type": "Cache", > >- "forward_snoops": true, > > "writeback_clean": false, > > "hit_latency": 2, > >+ "demand_mshr_reserve": 1, > > "tgts_per_mshr": 20, > >- "demand_mshr_reserve": 1, > > "addr_ranges": [ > > "0:18446744073709551615" > > ], > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout > >--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simoutFri > >May 06 17:00:54 2016 -0400 > >+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simoutSat > >May 07 14:43:06 2016 -0400 > >@@ -1,9 +1,9 @@ > > gem5 Simulator System. http://gem5.org > > gem5 is copyrighted software; use the --copyright option for details. > > > >-gem5 compiled Feb 1 2016 02:06:47 > >-gem5 started Feb 1 2016 02:07:02 > >-gem5 executing on zizzer, pid 44728 > >+gem5 compiled May 7 2016 13:41:33 > >+gem5 started May 7 2016 13:42:14 > >+gem5 executing on zizzer, pid 51342 > > command line: build/ALPHA/gem5.opt -d > >build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re > >/z/stever/hg/gem5/tests/run.py > >build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing > > > > Global frequency set at 1000000000000 ticks per second > >diff -r 517ba946a860 -r a22c4bac7e15 > >tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt > >--- > >a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txtFri > >May 06 17:00:54 2016 -0400 > >+++ > >b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txtSat > >May 07 14:43:06 2016 -0400 > >@@ -4,11 +4,11 @@ > > sim_ticks 733071500 > > # Number of ticks simulated > > final_tick 733071500 > > # Number of ticks from beginning of simulation (restored from > >checkpoints and never reset) > > sim_freq 1000000000000 > > # Frequency of simulated ticks > >-host_inst_rate 728390 > > # Simulator instruction rate (inst/s) > >-host_op_rate 728363 > > # Simulator op (including micro ops) rate (op/s) > >-host_tick_rate 1067851383 > > # Simulator tick rate (ticks/s) > >-host_mem_usage 229580 > > # Number of bytes of host memory used > >-host_seconds 0.69 > > # Real time elapsed on the host > >+host_inst_rate 558953 > > # Simulator instruction rate (inst/s) > >+host_op_rate 558933 > > # Simulator op (including micro ops) rate (op/s) > >+host_tick_rate 819448941 > > # Simulator tick rate (ticks/s) > >+host_mem_usage 229836 > > # Number of bytes of host memory used > >+host_seconds 0.89 > > # Real time elapsed on the host > > sim_insts 500001 > > # Number of instructions simulated > > sim_ops 500001 > > # Number of ops (including micro ops) simulated > > system.voltage_domain.voltage 1 > > # Voltage in Volts > >@@ -191,8 +191,6 @@ > > system.cpu.dcache.blocked::no_targets 0 > > # number of cycles access was blocked > > system.cpu.dcache.avg_blocked_cycles::no_mshrs nan > > # average number of cycles each access was blocked > > system.cpu.dcache.avg_blocked_cycles::no_targets nan > > # average number of cycles each access was blocked > >-system.cpu.dcache.fast_writes 0 > > # number of fast writes performed > >-system.cpu.dcache.cache_copies 0 > > # number of cache copies performed > > system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 > > # number of ReadReq MSHR misses > > system.cpu.dcache.ReadReq_mshr_misses::total 315 > > # number of ReadReq MSHR misses > > system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 > > # number of WriteReq MSHR misses > >@@ -225,7 +223,6 @@ > > system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 > > # average overall mshr miss latency > > system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 > > # average overall mshr miss latency > > system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 > > # average overall mshr miss latency > >-system.cpu.dcache.no_allocate_misses 0 > > # Number of misses that were no-allocate > > system.cpu.icache.tags.replacements 0 > > # number of replacements > > system.cpu.icache.tags.tagsinuse 264.585152 > > # Cycle average of tags in use > > system.cpu.icache.tags.total_refs 499617 > > # Total number of references to valid blocks. > >@@ -282,8 +279,6 @@ > > system.cpu.icache.blocked::no_targets 0 > > # number of cycles access was blocked > > system.cpu.icache.avg_blocked_cycles::no_mshrs nan > > # average number of cycles each access was blocked > > system.cpu.icache.avg_blocked_cycles::no_targets nan > > # average number of cycles each access was blocked > >-system.cpu.icache.fast_writes 0 > > # number of fast writes performed > >-system.cpu.icache.cache_copies 0 > > # number of cache copies performed > > system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 > > # number of ReadReq MSHR misses > > system.cpu.icache.ReadReq_mshr_misses::total 403 > > # number of ReadReq MSHR misses > > system.cpu.icache.demand_mshr_misses::cpu.inst 403 > > # number of demand (read+write) MSHR misses > >@@ -308,7 +303,6 @@ > > system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 > > # average overall mshr miss latency > > system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 > > # average overall mshr miss latency > > system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 > > # average overall mshr miss latency > >-system.cpu.icache.no_allocate_misses 0 > > # Number of misses that were no-allocate > > system.cpu.l2cache.tags.replacements 0 > > # number of replacements > > system.cpu.l2cache.tags.tagsinuse 480.680597 > > # Cycle average of tags in use > > system.cpu.l2cache.tags.total_refs 0 > > # Total number of references to valid blocks. > >@@ -393,8 +387,6 @@ > > system.cpu.l2cache.blocked::no_targets 0 > > # number of cycles access was blocked > > system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan > > # average number of cycles each access was blocked > > system.cpu.l2cache.avg_blocked_cycles::no_targets nan > > # average number of cycles each access was blocked > >-system.cpu.l2cache.fast_writes 0 > > # number of fast writes performed > >-system.cpu.l2cache.cache_copies 0 > > # number of cache copies performed > > system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 > > # number of ReadExReq MSHR misses > > system.cpu.l2cache.ReadExReq_mshr_misses::total 139 > > # number of ReadExReq MSHR misses > > system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 > > # number of ReadCleanReq MSHR misses > >@@ -443,7 +435,6 @@ > > system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 > > # average overall mshr miss latency > > system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 > > # average overall mshr miss latency > > system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 > > # average overall mshr miss latency > >_______________________________________________ > >gem5-dev mailing list > >[email protected] > >http://m5sim.org/mailman/listinfo/gem5-dev > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
