Hi everyone,
This patch has been sitting on the review board for almost a month now.
Nathanaël gave it the "ship it" and it was discussed a bit.
Since the change is minor (and has no effect on default O3CPU
configuration), do you think it is ready to be pushed, or does someone
disagree with the changes?
Cheers,
Arthur.
Le 05/05/2016 15:01, Nathanael Premillieu a écrit :
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3453/
Ship it!
Ship It!
- Nathanael Premillieu
On April 26th, 2016, 12:42 p.m. UTC, Arthur Perais wrote:
Review request for Default.
By Arthur Perais.
/Updated April 26, 2016, 12:42 p.m./
*Repository: * gem5
Description
Changeset 11459:faf70a6f13ed
o3: Clarify meaning of cachePorts variable in lsq_unit.hh
cachePorts currently constrains the number of store packets written to
the D-Cache each cycle), but loads currently affect this variable.
This leads to unexpected congestion (e.g., setting cachePorts to a
realistic 1 will in fact allow a store to WB only if no loads have
accessed the D-Cache this cycle). In the absence of arbitration, this
patch decouples how many loads can be done per cycle from how many
stores can be done per cycle.
Testing
util/regress -v --builds=ARM passes with 0% differences (expected:
cachePorts defaults to 200, so functionally, the patch changes nothing
for the default parameters).
Diffs
* src/cpu/o3/O3CPU.py (91834ba4b16d)
* src/cpu/o3/lsq_unit.hh (91834ba4b16d)
* src/cpu/o3/lsq_unit_impl.hh (91834ba4b16d)
View Diff <http://reviews.gem5.org/r/3453/diff/>
--
Arthur Perais
INRIA Bretagne Atlantique
Bâtiment 12E, Bureau E303, Campus de Beaulieu
35042 Rennes, France
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