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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3449/
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(Updated June 4, 2016, 12:25 p.m.)


Review request for Default.


Changes
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Rebase against latest gem5 and against latest mc2lib.


Repository: gem5


Description
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Add support for McVerSi memory consistency verification framework

This patch implements the Gem5-specific portion of McVerSi (a framework for 
simulation-based memory consistency verification) [1].

Architectures supported are:
- ARM (current mc2lib code generation only supports ARMv7).
- X86 (pseudo ops available via mmapped IPR interface).

Currently, only the O3CPU is supported.

[1] http://ac.marcoelver.com/research/mcversi


Diffs (updated)
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  util/m5/m5op.h e18a6c55bec0 
  util/m5/m5op_x86.S e18a6c55bec0 
  util/m5/m5ops.h e18a6c55bec0 
  src/sim/SConscript e18a6c55bec0 
  src/sim/mcversi.hh PRE-CREATION 
  src/sim/mcversi.cc PRE-CREATION 
  src/sim/pseudo_inst.hh e18a6c55bec0 
  src/sim/pseudo_inst.cc e18a6c55bec0 
  src/arch/arm/isa/formats/aarch64.isa e18a6c55bec0 
  src/arch/arm/isa/formats/m5ops.isa e18a6c55bec0 
  src/arch/arm/isa/insts/m5ops.isa e18a6c55bec0 
  src/cpu/o3/commit_impl.hh e18a6c55bec0 
  src/cpu/o3/dyn_inst.hh e18a6c55bec0 
  src/cpu/o3/dyn_inst_impl.hh e18a6c55bec0 
  src/cpu/o3/lsq_unit_impl.hh e18a6c55bec0 

Diff: http://reviews.gem5.org/r/3449/diff/


Testing
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Unless explicitly enabled (via loading appropriate workload), this component is 
unused.

Tested with ARM+Classic and X86+Ruby. Precompiled workloads that were used for 
testing available here: 
http://ac.marcoelver.com/res/mcversi_guest_workload_gem5.tar.gz

However, bugs have been found elsewhere in Gem5 while testing McVerSi (see 
http://www.mail-archive.com/[email protected]/msg18940.html , and 1 of 2 bugs 
from paper http://reviews.gem5.org/r/2842/ ). (I will not restate them here to 
keep the discussion on topic.)


Thanks,

Marco Elver

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