changeset 6319a1125f1c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6319a1125f1c
description:
cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <[email protected]>
diffstat:
src/arch/arm/isa.cc | 4 ++--
src/arch/arm/tlb.cc | 11 ++++++-----
src/arch/generic/memhelpers.hh | 8 ++++----
src/arch/x86/memhelpers.hh | 10 ++++++----
src/arch/x86/tlb.cc | 2 +-
src/cpu/base_dyn_inst.hh | 14 ++++++++------
src/cpu/checker/cpu.cc | 5 +++--
src/cpu/checker/cpu.hh | 7 ++++---
src/cpu/exec_context.hh | 7 ++++---
src/cpu/minor/exec_context.hh | 5 +++--
src/cpu/minor/lsq.cc | 3 ++-
src/cpu/minor/lsq.hh | 3 ++-
src/cpu/simple/atomic.cc | 11 ++++++-----
src/cpu/simple/atomic.hh | 8 +++++---
src/cpu/simple/base.hh | 7 ++++---
src/cpu/simple/exec_context.hh | 7 ++++---
src/cpu/simple/timing.cc | 7 ++++---
src/cpu/simple/timing.hh | 7 ++++---
18 files changed, 72 insertions(+), 54 deletions(-)
diffs (truncated from 520 to 300 lines):
diff -r b2720503a978 -r 6319a1125f1c src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Sat Aug 13 23:07:28 2016 -0400
+++ b/src/arch/arm/isa.cc Mon Aug 15 12:00:35 2016 +0100
@@ -1465,7 +1465,7 @@
case MISCREG_ATS1HR:
case MISCREG_ATS1HW:
{
- unsigned flags = 0;
+ Request::Flags flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
Fault fault;
@@ -1710,7 +1710,7 @@
case MISCREG_AT_S1E3W_Xt:
{
RequestPtr req = new Request;
- unsigned flags = 0;
+ Request::Flags flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
Fault fault;
diff -r b2720503a978 -r 6319a1125f1c src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Sat Aug 13 23:07:28 2016 -0400
+++ b/src/arch/arm/tlb.cc Mon Aug 15 12:00:35 2016 +0100
@@ -64,6 +64,7 @@
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "mem/page_table.hh"
+#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
@@ -555,7 +556,7 @@
vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
- uint32_t flags = req->getFlags();
+ Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
@@ -588,7 +589,7 @@
TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
{
Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
- uint32_t flags = req->getFlags();
+ Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
bool is_priv = isPriv && !(flags & UserMode);
@@ -760,7 +761,7 @@
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
- uint32_t flags = req->getFlags();
+ Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode);
@@ -967,7 +968,7 @@
vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
- uint32_t flags = req->getFlags();
+ Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
@@ -981,7 +982,7 @@
isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
- "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
+ "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2,
scr, sctlr, flags, tranType);
if ((req->isInstFetch() && (!sctlr.i)) ||
diff -r b2720503a978 -r 6319a1125f1c src/arch/generic/memhelpers.hh
--- a/src/arch/generic/memhelpers.hh Sat Aug 13 23:07:28 2016 -0400
+++ b/src/arch/generic/memhelpers.hh Mon Aug 15 12:00:35 2016 +0100
@@ -54,7 +54,7 @@
template <class XC, class MemT>
Fault
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
- MemT &mem, unsigned flags)
+ MemT &mem, Request::Flags flags)
{
return xc->initiateMemRead(addr, sizeof(MemT), flags);
}
@@ -73,7 +73,7 @@
template <class XC, class MemT>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
- unsigned flags)
+ Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
@@ -89,7 +89,7 @@
template <class XC, class MemT>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
- unsigned flags, uint64_t *res)
+ Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
@@ -102,7 +102,7 @@
template <class XC, class MemT>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
- Addr addr, unsigned flags, uint64_t *res)
+ Addr addr, Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
diff -r b2720503a978 -r 6319a1125f1c src/arch/x86/memhelpers.hh
--- a/src/arch/x86/memhelpers.hh Sat Aug 13 23:07:28 2016 -0400
+++ b/src/arch/x86/memhelpers.hh Mon Aug 15 12:00:35 2016 +0100
@@ -45,7 +45,7 @@
template <class XC>
Fault
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
- unsigned dataSize, unsigned flags)
+ unsigned dataSize, Request::Flags flags)
{
return xc->initiateMemRead(addr, dataSize, flags);
}
@@ -100,7 +100,7 @@
template <class XC>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
- unsigned dataSize, unsigned flags)
+ unsigned dataSize, Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
@@ -142,7 +142,8 @@
template <class XC>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
- unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+ unsigned dataSize, Addr addr, Request::Flags flags,
+ uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
@@ -176,7 +177,8 @@
template <class XC>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
- unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+ unsigned dataSize, Addr addr, Request::Flags flags,
+ uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
diff -r b2720503a978 -r 6319a1125f1c src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Sat Aug 13 23:07:28 2016 -0400
+++ b/src/arch/x86/tlb.cc Mon Aug 15 12:00:35 2016 +0100
@@ -273,7 +273,7 @@
TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
Mode mode, bool &delayedResponse, bool timing)
{
- uint32_t flags = req->getFlags();
+ Request::Flags flags = req->getFlags();
int seg = flags & SegmentFlagMask;
bool storeCheck = flags & (StoreCheck << FlagShift);
diff -r b2720503a978 -r 6319a1125f1c src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Sat Aug 13 23:07:28 2016 -0400
+++ b/src/cpu/base_dyn_inst.hh Mon Aug 15 12:00:35 2016 +0100
@@ -65,6 +65,7 @@
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
+#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
@@ -313,10 +314,10 @@
cpu->demapPage(vaddr, asn);
}
- Fault initiateMemRead(Addr addr, unsigned size, unsigned flags);
+ Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
- Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size, Addr addr,
+ Request::Flags flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -873,7 +874,8 @@
template<class Impl>
Fault
-BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
+BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
+ Request::Flags flags)
{
instFlags[ReqMade] = true;
Request *req = NULL;
@@ -925,8 +927,8 @@
template<class Impl>
Fault
-BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
+ Request::Flags flags, uint64_t *res)
{
if (traceData)
traceData->setMem(addr, size, flags);
diff -r b2720503a978 -r 6319a1125f1c src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Sat Aug 13 23:07:28 2016 -0400
+++ b/src/cpu/checker/cpu.cc Mon Aug 15 12:00:35 2016 +0100
@@ -139,7 +139,8 @@
}
Fault
-CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
+CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
+ Request::Flags flags)
{
Fault fault = NoFault;
int fullSize = size;
@@ -225,7 +226,7 @@
Fault
CheckerCPU::writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+ Addr addr, Request::Flags flags, uint64_t *res)
{
Fault fault = NoFault;
bool checked_flags = false;
diff -r b2720503a978 -r 6319a1125f1c src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Sat Aug 13 23:07:28 2016 -0400
+++ b/src/cpu/checker/cpu.hh Mon Aug 15 12:00:35 2016 +0100
@@ -57,6 +57,7 @@
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "debug/Checker.hh"
+#include "mem/request.hh"
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
@@ -374,9 +375,9 @@
}
Fault readMem(Addr addr, uint8_t *data, unsigned size,
- unsigned flags) override;
- Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res) override;
+ Request::Flags flags) override;
+ Fault writeMem(uint8_t *data, unsigned size, Addr addr,
+ Request::Flags flags, uint64_t *res) override;
unsigned int readStCondFailures() const override {
return thread->readStCondFailures();
diff -r b2720503a978 -r 6319a1125f1c src/cpu/exec_context.hh
--- a/src/cpu/exec_context.hh Sat Aug 13 23:07:28 2016 -0400
+++ b/src/cpu/exec_context.hh Mon Aug 15 12:00:35 2016 +0100
@@ -51,6 +51,7 @@
#include "cpu/base.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
+#include "mem/request.hh"
/**
* The ExecContext is an abstract base class the provides the
@@ -182,7 +183,7 @@
* should never be called).
*/
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
- unsigned int flags)
+ Request::Flags flags)
{
panic("ExecContext::readMem() should be overridden\n");
}
@@ -195,7 +196,7 @@
* should never be called).
*/
virtual Fault initiateMemRead(Addr addr, unsigned int size,
- unsigned int flags)
+ Request::Flags flags)
{
panic("ExecContext::initiateMemRead() should be overridden\n");
}
@@ -205,7 +206,7 @@
* For timing-mode contexts, initiate a timing memory write operation.
*/
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
- unsigned int flags, uint64_t *res) = 0;
+ Request::Flags flags, uint64_t *res) = 0;
/**
* Sets the number of consecutive store conditional failures.
diff -r b2720503a978 -r 6319a1125f1c src/cpu/minor/exec_context.hh
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