On 26/08/2016 09:58, Bjoern A. Zeeb wrote:
On 25 Aug 2016, at 22:09, Andreas Hansson wrote:
Hi all,
Thanks a lot for that reply.
Two thoughts:
1. Does X86 + o3 + classic memory system actually work?
2. The interleaving of “real” timing accesses and the functional “debug”
accesses is not well defined. In general I would encourage to not assume
anything.
If you are indeed using classic (see 1), then I think I know what is
causing the issue. In functional cache accesses we check the cache
itself
before we check the MSHRs. Thus, if a write is done from the perspective
of the LSQ, you won’t necessarily see it by means of the functional
access. Is it a bug (see 2), we’d have to decide?
I think that might be related to the only(1) other issue I see on x86
+ o3 + classic.
How can we fix this? Why is it not an issue on ARM (which does the
same)? Is it because there you only have a the register but no memory
access?
I think the fact that ARM uses a register is what saves us. A quick look
at the O3 code suggests that we could call a PCEvent before a memory
access has been sent to the L1 cache. This effectively hides the write
to the stack from the functional access in your code.
I don't know the best solution for this particular issue. I suspect that
we will need to handle functional accesses in the LSQ and implement
functional reads from the store queue. Doing this will be "interesting"
though since we the simulated wire delay between commit and IEW/LSQ
means that we won't know that an instruction has committed until a few
cycles after the PCEvent fires.
//Andreas
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
