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(Updated Sept. 29, 2016, 6:59 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11657:f8e054c9d0d6 --------------------------- riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fix exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] Signed-off by: Alec Roelke Diffs (updated) ----- src/arch/riscv/faults.hh PRE-CREATION src/arch/riscv/faults.cc PRE-CREATION src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/formats.isa PRE-CREATION src/arch/riscv/isa/formats/fp.isa PRE-CREATION src/arch/riscv/isa/includes.isa PRE-CREATION src/arch/riscv/isa/operands.isa PRE-CREATION src/arch/riscv/registers.hh PRE-CREATION src/arch/riscv/utility.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3628/diff/ Testing ------- Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
