> On Aug. 17, 2016, 10:35 a.m., Andreas Hansson wrote: > > No objections. We have been thinking of making this simpler, by creating a > > notion of PortGroups, and let the group be responsible for any > > hash/interleaving. Until we actually get to the point of implementing this > > I agree that we should proceed with your patch.
Should this be marked submitted? Also, was the CXX parser updated to accommodate the change? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3604/#review8646 ----------------------------------------------------------- On Aug. 4, 2016, 5:56 p.m., Matthew Poremba wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3604/ > ----------------------------------------------------------- > > (Updated Aug. 4, 2016, 5:56 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11594:805067369ea7 > --------------------------- > base: Output all AddrRange parameters to config.ini > > Currently only 'start' and 'end' of AddrRange are printed in config.ini. > This causes address ranges to be overlapping when loading a c++-only > config with interleaved addresses using CxxConfigManger. This patch adds > prints for the interleave and XOR bits to config.ini such that address > ranges are properly setup with cxx config. > > > Diffs > ----- > > src/python/m5/params.py ba45735a726a4582e63561ab3dc741d7f0890447 > > Diff: http://reviews.gem5.org/r/3604/diff/ > > > Testing > ------- > > > Thanks, > > Matthew Poremba > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
