Hello, Could you give us some more details on what you're proposing. What is this "component"? Do you expect that many people in the community will need/want to use this component? If so, then it may make sense to incorporate some changes to the BaseCPU object.
The way I see it is you have three high-level options: 1) Make changes to the BaseCPU. This will likely be the most work to get the community to accept. Unless it's a change that almost everyone will be using, I doubt we will want to incorporate it. 2) Make your changes very modular. Modular in the sense that if someone wants to use gem5 without using your new component they'll never knew you added it. This should be more that just adding a default "off" parameter. The key goal is to be the least invasive as possible. 3) Post your code on a fork of gem5. Sometimes you have to make major modifications to central components to complete your research objective. In this case, it may be better just to post your code somewhere like github. Or to go the route we did with gem5-gpu and make it an "external" component. Though this has the drawback of trying to keep it up to date with the mainline. In conclusion, if you can give us more information we'll be able to guide you better. Cheers, Jason On Tue, Oct 25, 2016 at 9:29 AM Pierre-Yves Péneau < pierre-yves.pen...@lirmm.fr> wrote: > Hi all, > > I would like to add a new hardware component in gem5. This component > will be at the same level than L1 caches. I am planning to modify the > base cpu to add a new port and use it to communicate with my component. > > Eventually, I would like to share my work with the gem5 community. > Louisa Bessad (from my lab) had a discussion with Gabor Dozsa from ARM > and told me that any modification to the base cpu must be strongly > justified to the developers, and so could be very hard to merge in gem5. > > So, my questions are: > - can I do what I want without modifying the base cpu ? > - if not, what are the chances that my work will be accepted ? > > Thank you all. > > -- > +-------------------------------------------------------------+ > | Pierre-Yves Péneau - PhD student | first.last at lirmm.fr | > | LIRMM / CNRS - SYSMIC team | + 33 4 67 41 86 33 > <+33%204%2067%2041%2086%2033> | > | Building 4 Office H2.2 | http://walafc0.org | > +-------------------------------------------------------------+ > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
