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Review request for Default. Repository: gem5 Description ------- cpu: Add a SynchroTrace replay model SynchroTrace's trace replay is a 1-CPI timing model that interfaces with the multi-threaded traces from Sigil to inject traffic into the detailed memory model. The high-level description of the execution flow is in src/cpu/testers/synchrotrace/SynchroTrace.hh The following is included in this patch: * The main SynchroTrace trace replay file * SynchroTrace parser file which processes Sigil Traces into SynchroTrace events * A front-end python configuration script with a default two-level cache hierarchy. Change-Id: I6c89894d95974d838bc9ee3b9e468a4032f6613a Diffs ----- configs/example/synchrotrace_classic_memory.py PRE-CREATION src/cpu/testers/synchrotrace/SConscript PRE-CREATION src/cpu/testers/synchrotrace/SynchroTrace.py PRE-CREATION src/cpu/testers/synchrotrace/st_event.hh PRE-CREATION src/cpu/testers/synchrotrace/st_parser.hh PRE-CREATION src/cpu/testers/synchrotrace/st_parser.cc PRE-CREATION src/cpu/testers/synchrotrace/synchro_trace.hh PRE-CREATION src/cpu/testers/synchrotrace/synchro_trace.cc PRE-CREATION Diff: http://reviews.gem5.org/r/3687/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
