changeset c7453f485a5f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7453f485a5f
description:
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file,
or are
an immediate.
for machine ISA, however, an op selector may specify special registers,
or
may specify special SGPRs with an alias op selector value. the location
of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the
relative
positions of the special register values.
diffstat:
src/arch/hsail/insts/branch.hh | 12 +++++-
src/arch/hsail/insts/decl.hh | 44 +++++++++++++++++++++++-----
src/arch/hsail/insts/mem.hh | 18 +++++++---
src/gpu-compute/condition_register_state.cc | 6 +-
src/gpu-compute/condition_register_state.hh | 2 +-
src/gpu-compute/gpu_dyn_inst.cc | 10 +++++-
src/gpu-compute/gpu_dyn_inst.hh | 3 +-
src/gpu-compute/gpu_static_inst.hh | 13 +++++++-
src/gpu-compute/vector_register_file.cc | 6 +-
9 files changed, 84 insertions(+), 30 deletions(-)
diffs (truncated from 341 to 300 lines):
diff -r d1ad31187fa5 -r c7453f485a5f src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hh Wed Oct 26 22:47:47 2016 -0400
+++ b/src/arch/hsail/insts/branch.hh Wed Oct 26 22:47:49 2016 -0400
@@ -95,7 +95,9 @@
return target.opSize();
}
- int getRegisterIndex(int operandIndex) override {
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+ {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}
@@ -223,7 +225,9 @@
else
return 1;
}
- int getRegisterIndex(int operandIndex) override {
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+ {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.regIndex();
@@ -370,7 +374,9 @@
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize();
}
- int getRegisterIndex(int operandIndex) override {
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+ {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}
diff -r d1ad31187fa5 -r c7453f485a5f src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh Wed Oct 26 22:47:47 2016 -0400
+++ b/src/arch/hsail/insts/decl.hh Wed Oct 26 22:47:49 2016 -0400
@@ -178,7 +178,9 @@
else
return dest.opSize();
}
- int getRegisterIndex(int operandIndex) {
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (operandIndex < NumSrcOperands)
@@ -313,7 +315,10 @@
else
return dest.opSize();
}
- int getRegisterIndex(int operandIndex) {
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex)
return src0.regIndex();
@@ -477,7 +482,10 @@
else
return dest.opSize();
}
- int getRegisterIndex(int operandIndex) {
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex)
return src0.regIndex();
@@ -643,7 +651,7 @@
return -1;
//handle positive and negative numbers
- T tmp = (src0 < 0) ? (~src0) : (src0);
+ T tmp = ((int64_t)src0 < 0) ? (~src0) : (src0);
//the starting pos is MSB
int pos = 8 * sizeof(T) - 1;
@@ -732,7 +740,12 @@
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
- int getRegisterIndex(int operandIndex) { return -1; }
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
+ return -1;
+ }
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return 0; }
@@ -777,10 +790,14 @@
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.opSize();
}
- int getRegisterIndex(int operandIndex) {
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.regIndex();
}
+
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return dest.isVectorRegister(); }
int getNumOperands() { return 1; }
@@ -848,10 +865,14 @@
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.opSize();
}
- int getRegisterIndex(int operandIndex) {
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.regIndex();
}
+
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return dest.isVectorRegister(); }
int getNumOperands() { return 1; }
@@ -1171,8 +1192,13 @@
bool isScalarRegister(int operandIndex) { return false; }
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
- int getOperandSize(int operandIndex) { return 0; }
- int getRegisterIndex(int operandIndex) { return -1; }
+ int getOperandSize(int operandIndex) { return 0; }
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ {
+ return -1;
+ }
void
execute(GPUDynInstPtr gpuDynInst)
diff -r d1ad31187fa5 -r c7453f485a5f src/arch/hsail/insts/mem.hh
--- a/src/arch/hsail/insts/mem.hh Wed Oct 26 22:47:47 2016 -0400
+++ b/src/arch/hsail/insts/mem.hh Wed Oct 26 22:47:49 2016 -0400
@@ -146,7 +146,8 @@
return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize());
}
- int getRegisterIndex(int operandIndex) override
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() :
@@ -377,7 +378,8 @@
return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize());
}
- int getRegisterIndex(int operandIndex) override
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() :
@@ -670,7 +672,8 @@
AddrOperandType>::dest.opSize());
return 0;
}
- int getRegisterIndex(int operandIndex) override
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) &&
@@ -934,7 +937,8 @@
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.opSize() : this->addr.opSize();
}
- int getRegisterIndex(int operandIndex) override
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.regIndex() : this->addr.regIndex();
@@ -1144,7 +1148,8 @@
AddrOperandType>::src.opSize();
return 0;
}
- int getRegisterIndex(int operandIndex) override
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands)
@@ -1433,7 +1438,8 @@
else
return(dest.opSize());
}
- int getRegisterIndex(int operandIndex)
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex < NumSrcOperands)
diff -r d1ad31187fa5 -r c7453f485a5f src/gpu-compute/condition_register_state.cc
--- a/src/gpu-compute/condition_register_state.cc Wed Oct 26 22:47:47
2016 -0400
+++ b/src/gpu-compute/condition_register_state.cc Wed Oct 26 22:47:49
2016 -0400
@@ -62,19 +62,19 @@
}
void
-ConditionRegisterState::exec(GPUStaticInst *ii, Wavefront *w)
+ConditionRegisterState::exec(GPUDynInstPtr ii, Wavefront *w)
{
// iterate over all operands
for (auto i = 0; i < ii->getNumOperands(); ++i) {
// is this a condition register destination operand?
if (ii->isCondRegister(i) && ii->isDstOperand(i)) {
// mark the register as busy
- markReg(ii->getRegisterIndex(i), 1);
+ markReg(ii->getRegisterIndex(i, ii), 1);
uint32_t pipeLen = w->computeUnit->spBypassLength();
// schedule an event for marking the register as ready
w->computeUnit->
- registerEvent(w->simdId, ii->getRegisterIndex(i),
+ registerEvent(w->simdId, ii->getRegisterIndex(i, ii),
ii->getOperandSize(i),
w->computeUnit->shader->tick_cnt +
w->computeUnit->shader->ticks(pipeLen), 0);
diff -r d1ad31187fa5 -r c7453f485a5f src/gpu-compute/condition_register_state.hh
--- a/src/gpu-compute/condition_register_state.hh Wed Oct 26 22:47:47
2016 -0400
+++ b/src/gpu-compute/condition_register_state.hh Wed Oct 26 22:47:49
2016 -0400
@@ -87,7 +87,7 @@
}
int numRegs() { return c_reg.size(); }
- void exec(GPUStaticInst *ii, Wavefront *w);
+ void exec(GPUDynInstPtr ii, Wavefront *w);
private:
ComputeUnit* computeUnit;
diff -r d1ad31187fa5 -r c7453f485a5f src/gpu-compute/gpu_dyn_inst.cc
--- a/src/gpu-compute/gpu_dyn_inst.cc Wed Oct 26 22:47:47 2016 -0400
+++ b/src/gpu-compute/gpu_dyn_inst.cc Wed Oct 26 22:47:49 2016 -0400
@@ -102,10 +102,16 @@
return _staticInst->isScalarRegister(operandIdx);
}
+bool
+GPUDynInst::isCondRegister(int operandIdx)
+{
+ return _staticInst->isCondRegister(operandIdx);
+}
+
int
-GPUDynInst::getRegisterIndex(int operandIdx)
+GPUDynInst::getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst)
{
- return _staticInst->getRegisterIndex(operandIdx);
+ return _staticInst->getRegisterIndex(operandIdx, gpuDynInst);
}
int
diff -r d1ad31187fa5 -r c7453f485a5f src/gpu-compute/gpu_dyn_inst.hh
--- a/src/gpu-compute/gpu_dyn_inst.hh Wed Oct 26 22:47:47 2016 -0400
+++ b/src/gpu-compute/gpu_dyn_inst.hh Wed Oct 26 22:47:49 2016 -0400
@@ -194,7 +194,8 @@
int getNumOperands();
bool isVectorRegister(int operandIdx);
bool isScalarRegister(int operandIdx);
- int getRegisterIndex(int operandIdx);
+ bool isCondRegister(int operandIdx);
+ int getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst);
int getOperandSize(int operandIdx);
bool isDstOperand(int operandIdx);
bool isSrcOperand(int operandIdx);
diff -r d1ad31187fa5 -r c7453f485a5f src/gpu-compute/gpu_static_inst.hh
--- a/src/gpu-compute/gpu_static_inst.hh Wed Oct 26 22:47:47 2016 -0400
+++ b/src/gpu-compute/gpu_static_inst.hh Wed Oct 26 22:47:49 2016 -0400
@@ -83,7 +83,10 @@
virtual bool isSrcOperand(int operandIndex) = 0;
virtual bool isDstOperand(int operandIndex) = 0;
virtual int getOperandSize(int operandIndex) = 0;
- virtual int getRegisterIndex(int operandIndex) = 0;
+
+ virtual int getRegisterIndex(int operandIndex,
+ GPUDynInstPtr gpuDynInst) = 0;
+
virtual int numDstRegOperands() = 0;
virtual int numSrcRegOperands() = 0;
@@ -286,7 +289,13 @@
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
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