changeset 3027d6c34fa4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3027d6c34fa4
description:
gpu-compute, arch: add some methods to the base inst classes for ISA
support
diffstat:
src/arch/hsail/insts/gpu_static_inst.hh | 1 +
src/gpu-compute/gpu_static_inst.hh | 9 +++++++++
2 files changed, 10 insertions(+), 0 deletions(-)
diffs (37 lines):
diff -r 9d19bb965564 -r 3027d6c34fa4 src/arch/hsail/insts/gpu_static_inst.hh
--- a/src/arch/hsail/insts/gpu_static_inst.hh Wed Oct 26 22:46:58 2016 -0400
+++ b/src/arch/hsail/insts/gpu_static_inst.hh Wed Oct 26 22:47:01 2016 -0400
@@ -56,6 +56,7 @@
void generateDisassembly();
const std::string &disassemble();
uint32_t instSize() { return 4; }
+ bool isValid() const override { return true; }
protected:
HsailCode *hsailCode;
diff -r 9d19bb965564 -r 3027d6c34fa4 src/gpu-compute/gpu_static_inst.hh
--- a/src/gpu-compute/gpu_static_inst.hh Wed Oct 26 22:46:58 2016 -0400
+++ b/src/gpu-compute/gpu_static_inst.hh Wed Oct 26 22:47:01 2016 -0400
@@ -84,6 +84,8 @@
virtual int numDstRegOperands() = 0;
virtual int numSrcRegOperands() = 0;
+ virtual bool isValid() const = 0;
+
/*
* Most instructions (including all HSAIL instructions)
* are vector ops, so _scalarOp will be false by default.
@@ -109,6 +111,13 @@
fatal("calling initiateAcc() on a non-memory instruction.\n");
}
+ // only used for memory instructions
+ virtual void
+ completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ fatal("calling completeAcc() on a non-memory instruction.\n");
+ }
+
virtual uint32_t getTargetPc() { return 0; }
/**
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