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Over the past few days I've been building a seventh patch to add to my original series of five (now six) that adds RISC-V to add regression tests for each instruction. In doing so I've discovered that the LLSC code I copied from MIPS may not have been sufficient for RISC-V's LR and SC instructions, the fact of which slipped through my tests during my initial implementation. Since this is a pretty big change, the read-modify-write instructions work fine (and so do LR and SC except for SC's success code result), and the fix also depends on patch 5, I'm going to leave this patch as it is and implement the corrections in a new patch that will come out before the regression patch. - Alec Roelke On Nov. 2, 2016, 2:36 a.m., Alec Roelke wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3629/ > ----------------------------------------------------------- > > (Updated Nov. 2, 2016, 2:36 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11691:27eb41480488 > --------------------------- > riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A > > Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A > extension, which includes atomic memory instructions. These instructions > atomically read a value from memory, modify it with a value contained in a > source register, and store the original memory value in the destination > register and modified value back into memory. Because this requires two > memory accesses and GEM5 does not support two timing memory accesses in > a single instruction, each of these instructions is split into two micro- > ops: A "load" micro-op, which reads the memory, and a "store" micro-op, > which modifies and writes it back. Each atomic memory instruction also has > two bits that acquire and release a lock on its memory location. > Additionally, there are atomic load and store instructions that only either > load or store, but not both, and can acquire or release memory locks. > > Note that because the current implementation of RISC-V only supports one > core and one thread, it doesn't make sense to make use of AMO instructions. > However, they do form a standard extension of the RISC-V ISA, so they are > included mostly as a placeholder for when multithreaded execution is > implemented. As a result, any tests for their correctness in a future > patch may be abbreviated. > > Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; > patch 2 implemented the integer multiply extension, RV64M; and patch 3 > implemented the single- and double-precision floating point extensions, > RV64FD. > > Patch 5 will add support for timing, minor, and detailed CPU models that > isn't present in patches 1-4. > > [Added missing file amo.isa] > [Replaced information removed from initial patch that was missed during > division into multiple patches.] > [Fixed some minor formatting issues.] > [Fixed oversight where LR and SC didn't have both AQ and RL flags.] > Signed-off by: Alec Roelke > > > Diffs > ----- > > src/arch/riscv/isa/bitfields.isa PRE-CREATION > src/arch/riscv/isa/decoder.isa PRE-CREATION > src/arch/riscv/isa/formats/amo.isa PRE-CREATION > src/arch/riscv/isa/formats/formats.isa PRE-CREATION > src/arch/riscv/isa/formats/mem.isa PRE-CREATION > src/arch/riscv/isa/main.isa PRE-CREATION > src/arch/riscv/isa/micro.isa PRE-CREATION > src/arch/riscv/isa/operands.isa PRE-CREATION > src/arch/riscv/registers.hh PRE-CREATION > src/arch/riscv/types.hh PRE-CREATION > > Diff: http://reviews.gem5.org/r/3629/diff/ > > > Testing > ------- > > > Thanks, > > Alec Roelke > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
