Hi Bjoern, Just add MinorCPU on the command line when compiling with scons: > scons build/X86/gem5.opt CPU_MODELS=AtomicSimpleCPU,O3CPU,TimingSimpleCPU,MinorCPU
Or, you could modify the default build options in build_opts/X86. Cheers, Jason On Fri, Dec 9, 2016 at 10:40 AM Bjoern A. Zeeb < bzeeb-li...@lists.zabbadoz.net> wrote: > On 23 Nov 2016, at 4:05, Ayaz Akram wrote: > > > Hi, > > > > I had posted a problem that I faced with x86 minor cpu regarding > > branch > > prediction on gem5 users mailing list (link of that post is given > > below): > > sorry for hijacking this; how do you get MinorCPU running on X86? > > I added printf during compilation and I do see: > > XXX-BZ supported CPU_MODELS: AtomicSimpleCPU,O3CPU,TimingSimpleCPU > XXX-BZ supported CPU_MODELS subst: AtomicSimpleCPU O3CPU TimingSimpleCPU > XXX-BZ CpuModel keys O3CPU > XXX-BZ CpuModel keys AtomicSimpleCPU > XXX-BZ CpuModel keys no > XXX-BZ CpuModel keys MinorCPU > XXX-BZ CpuModel keys CheckerCPU > XXX-BZ CpuModel keys TimingSimpleCPU > XXX-BZ CpuModel items O3CPU default 1 > XXX-BZ CpuModel items AtomicSimpleCPU default 1 > XXX-BZ CpuModel items no default 0 > XXX-BZ CpuModel items MinorCPU default 1 > XXX-BZ CpuModel items CheckerCPU default 0 > XXX-BZ CpuModel items TimingSimpleCPU default 1 > XXX-BZ sorted AtomicSimpleCPU > XXX-BZ sorted MinorCPU > XXX-BZ sorted O3CPU > XXX-BZ sorted TimingSimpleCPU > > When I do list the CPU types on X86 it’s not there (funnily the > arm_detail is listed unconditionally): > > $ ./build/X86/gem5.opt configs/example/fs.py --list-cpu-types > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > .. > command line: ./build/X86/gem5.opt configs/example/fs.py > --list-cpu-types > .. > Available CPU classes: > arm_detailed > AtomicSimpleCPU > Simple CPU model executing a configurable number of > instructions per > cycle. This model uses the simplified 'atomic' memory > mode. > TraceCPU > Trace CPU model which replays traces generated in a > prior simulation > using DerivO3CPU or its derived classes. It interfaces > with L1 > caches. > DerivO3CPU > TimingSimpleCPU > > CPU aliases: > timing => TimingSimpleCPU > detailed => DerivO3CPU > atomic => AtomicSimpleCPU > trace => TraceCPU > > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
