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Review request for Default. Repository: gem5 Description ------- Changeset 11765:5842520dead7 --------------------------- arch: ISA parser additions of vector registers Reiley's update :) of the isa parser definitions. My addition of the vector element operand concept for the ISA parser. Nathanael's modification creating a hierarchy between vector registers and its constituencies to the isa parser. Some fixes/updates on top to consider instructions as vectors instead of floating when they use the VectorRF. Some counters added to all the models to keep faithful counts. Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101 Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> Diffs ----- src/arch/alpha/faults.hh 78ef8daecd81 src/arch/alpha/faults.cc 78ef8daecd81 src/arch/alpha/isa/fp.isa 78ef8daecd81 src/arch/arm/insts/macromem.cc 78ef8daecd81 src/arch/arm/isa/insts/fp64.isa 78ef8daecd81 src/arch/arm/isa/insts/neon64.isa 78ef8daecd81 src/arch/arm/isa/operands.isa 78ef8daecd81 src/arch/arm/isa/templates/mem.isa 78ef8daecd81 src/arch/arm/isa/templates/pred.isa 78ef8daecd81 src/arch/isa_parser.py 78ef8daecd81 src/arch/sparc/faults.hh 78ef8daecd81 src/arch/sparc/faults.cc 78ef8daecd81 src/arch/sparc/isa/base.isa 78ef8daecd81 src/cpu/StaticInstFlags.py 78ef8daecd81 src/cpu/base_dyn_inst.hh 78ef8daecd81 src/cpu/o3/commit.hh 78ef8daecd81 src/cpu/o3/commit_impl.hh 78ef8daecd81 src/cpu/o3/inst_queue.hh 78ef8daecd81 src/cpu/o3/inst_queue_impl.hh 78ef8daecd81 src/cpu/simple/base.cc 78ef8daecd81 src/cpu/simple/exec_context.hh 78ef8daecd81 src/cpu/static_inst.hh 78ef8daecd81 Diff: http://reviews.gem5.org/r/3760/diff/ Testing ------- Builtin regressions Thanks, Rekai Gonzalez Alberquilla _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
