changeset af41594e9b3c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=af41594e9b3c
description:
sim: Remove redundant export_method_cxx_predecls
The headers declared in export_method_cxx_predecls are redundant since a
SimObject's main header is automatically included.
Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Curtis Dunham <[email protected]>
Reviewed-by: Joe Gross <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
diffstat:
src/arch/arm/ArmSystem.py | 4 ----
src/cpu/kvm/BaseKvmCPU.py | 4 ----
src/python/m5/SimObject.py | 12 +-----------
src/sim/System.py | 4 ----
4 files changed, 1 insertions(+), 23 deletions(-)
diffs (78 lines):
diff -r 6639b188ac11 -r af41594e9b3c src/arch/arm/ArmSystem.py
--- a/src/arch/arm/ArmSystem.py Tue Jan 03 11:31:46 2017 +0000
+++ b/src/arch/arm/ArmSystem.py Tue Jan 03 12:03:06 2017 +0000
@@ -99,10 +99,6 @@
cxx_header = "arch/arm/linux/system.hh"
@classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "arch/arm/linux/system.hh"')
-
- @classmethod
def export_methods(cls, code):
code('''void dumpDmesg();''')
diff -r 6639b188ac11 -r af41594e9b3c src/cpu/kvm/BaseKvmCPU.py
--- a/src/cpu/kvm/BaseKvmCPU.py Tue Jan 03 11:31:46 2017 +0000
+++ b/src/cpu/kvm/BaseKvmCPU.py Tue Jan 03 12:03:06 2017 +0000
@@ -47,10 +47,6 @@
abstract = True
@classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "cpu/kvm/base.hh"')
-
- @classmethod
def export_methods(cls, code):
code('''
void dump() const;
diff -r 6639b188ac11 -r af41594e9b3c src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py Tue Jan 03 11:31:46 2017 +0000
+++ b/src/python/m5/SimObject.py Tue Jan 03 12:03:06 2017 +0000
@@ -498,8 +498,7 @@
# suppresses inheritance by substituting in the base (null)
# versions of these methods unless a different version is
# explicitly supplied.
- for method_name in ('export_methods', 'export_method_cxx_predecls',
- 'export_method_swig_predecls'):
+ for method_name in ('export_methods', 'export_method_swig_predecls'):
if method_name not in cls.__dict__:
base_method = getattr(MetaSimObject, method_name)
m = MethodType(base_method, cls, MetaSimObject)
@@ -665,14 +664,6 @@
pass
# Generate the code needed as a prerequisite for the C++ methods
- # exported via export_methods() to be compiled in the _wrap.cc
- # file. Typically generates one or more #include statements. If
- # any methods are exported, typically at least the C++ header
- # declaring the relevant SimObject class must be included.
- def export_method_cxx_predecls(cls, code):
- pass
-
- # Generate the code needed as a prerequisite for the C++ methods
# exported via export_methods() to be processed by SWIG.
# Typically generates one or more %include or %import statements.
# If any methods are exported, typically at least the C++ header
@@ -703,7 +694,6 @@
for param in params:
param.cxx_predecls(code)
code('#include "${{cls.cxx_header}}"')
- cls.export_method_cxx_predecls(code)
code('''\
/**
* This is a workaround for bug in swig. Prior to gcc 4.6.1 the STL
diff -r 6639b188ac11 -r af41594e9b3c src/sim/System.py
--- a/src/sim/System.py Tue Jan 03 11:31:46 2017 +0000
+++ b/src/sim/System.py Tue Jan 03 12:03:06 2017 +0000
@@ -44,10 +44,6 @@
system_port = MasterPort("System port")
@classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "sim/system.hh"')
-
- @classmethod
def export_methods(cls, code):
code('''
Enums::MemoryMode getMemoryMode() const;
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