----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3816/#review9452 -----------------------------------------------------------
Ship it! Thanks for fixing this! The change looks functionally correct. However, the I'd appreciate it if you could restructure it slightly to remove the special case in the loop that updates miscregs. src/arch/arm/kvm/armv8_cpu.cc (line 193) <http://reviews.gem5.org/r/3816/#comment7972> This is a bit weird. I'd suggest that you remove PSTATE/CPSR from the miscRegMap and just handle it separately before this loop. If you do this, you'll have to sync it manually early in updateThreadContext() to make sure that gem5 is aware of the CPU state before syncing other registers. - Andreas Sandberg On Feb. 21, 2017, 4:55 p.m., Rahul Thakur wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3816/ > ----------------------------------------------------------- > > (Updated Feb. 21, 2017, 4:55 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11873:6069fbdacba5 > --------------------------- > commit 70469eba20cdcf091d66cf2ef463318203c7cc71 > Author: Slava Malyugin <slav...@google.com> > Date: Wed Dec 2 19:01:12 2015 -0800 > > arm, kvm: fix saving/restoring conditional flags in ARM KVM64 > > The gem5 stores flags separately from other fields CPSR, so we need to > split them out and recombine on trips to/from KVM. > > Change-Id: I9f0a685f8667c581cdef7d8c234604a3135d9402 > > > Diffs > ----- > > src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 > > Diff: http://reviews.gem5.org/r/3816/diff/ > > > Testing > ------- > > > Thanks, > > Rahul Thakur > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
