Anthony Gutierrez has uploaded this change for review. (
https://gem5-review.googlesource.com/3400
Change subject: x86: fix Mul1u instruction
......................................................................
x86: fix Mul1u instruction
the Mul1uFlags and Mul1u instructions perform
the 64b multiplication using only 64b registers, however the
method used causes the high 64b to be corrupted for certain
inputs. here we fix the computation.
Change-Id: I6118d5092da8a5368776a46a6e8b95a960146ab6
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index ef0c4cb..84f77e2 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -580,15 +580,17 @@
code = '''
ProdLow = psrc1 * op2;
- int halfSize = (dataSize * 8) / 2;
- uint64_t shifter = (ULL(1) << halfSize);
- uint64_t psrc1_h = psrc1 / shifter;
- uint64_t psrc1_l = psrc1 & mask(halfSize);
- uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
- uint64_t psrc2_l = op2 & mask(halfSize);
- ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
- ((psrc1_l * psrc2_l) / shifter)) / shifter) +
- psrc1_h * psrc2_h;
+ int shifter = (dataSize * 8) / 2;
+ uint64_t psrc1_h = (psrc1 >> shifter) & mask(shifter);
+ uint64_t psrc1_l = psrc1 & mask(shifter);
+ uint64_t psrc2_h = (op2 >> shifter) & mask(shifter);
+ uint64_t psrc2_l = op2 & mask(shifter);
+
+ ProdHi = psrc1_h * psrc2_h + ((psrc1_h * psrc2_l) >> shifter)
+ + ((psrc1_l * psrc2_h) >> shifter)
+ + ((((psrc1_l * psrc2_h) & 0xffffffff)
+ + ((psrc1_h * psrc2_l) & 0xffffffff)
+ + ((psrc1_l * psrc2_l) >> shifter)) >> shifter);
'''
flag_code = '''
if (ProdHi) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6118d5092da8a5368776a46a6e8b95a960146ab6
Gerrit-Change-Number: 3400
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez <[email protected]>
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