Hi Christian,
Thank you for the reply. I have configured the address ranges accordingly in my configuration script for both the external memory and SimpleMemory model. But I am unable to find a way to define a new address mapping. In SE mode, only SimpleMemory model (the one I am using for GEM5 memory) is being recognized as physical memory and it is the only one mapped (virtual to physical). An excerpt from my config.ini looks as follows (modified to include both memories) [system] type=System children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler physmem external_memory membus voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem mmap_using_noreserve=false multi_thread=false . . . [system.physmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true kvm_map=true latency=30000 latency_var=0 null=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.external_memory] type=ExternalSlave addr_ranges=134217728:671088639:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model=Null port=system.membus.master[1] . . . I will have a look at FS mode as well. The motivation to use the TLM-Bridge is because we will have more accelerators in SystemC, and we will like to plug them directly with the GEM5 world. Regards Yasir -----Original Message----- From: Christian Menard [mailto:christian.men...@tu-dresden.de] Sent: 19 June 2017 16:58 To: gem5-dev@gem5.org Cc: Qureshi Yasir Mahmood <yasir.qure...@epfl.ch> Subject: Re: [gem5-dev] GEM5-to-TLM Memory/Accelerator Access Hi Yasir, The short answer: You need to configure your gem5 simulation properly. You can configure address ranges in the ExternalSlave object (see src/mem/ ExternalSlave.py). You will also need to configure your MMU to implement the right address mappings. I am not sure how this works in SE mode, but there should be a way of defining new address mappings. You probably want to look at se.py and the files it imports and understand how the memory map is set up. Maybe you should also consider to switch to FS mode. While I appreciate your interest, I don't understand your motivation for using the TLM-Bridge. If you implement an accelerator from scratch, why don't you do so in gem5 directly? Why do you need the TLM bridge? I saw your e-mails on 'SystemC and GEM5 SE Mode' and will look into this issue when I find the time. Best regards, Christian Menard On Monday, 19 June 2017 16:14:27 CEST Qureshi Yasir Mahmood wrote: > Hi All, > > I am trying to setup a GEM5-to-TLM simulation with GEM5 in ARM SE mode > and SimpleMemory as the physical memory. I intend to model an > accelerator in SystemC in the TLM world. I want my accelerator to > start when I signal it through some memory mapped register > (effectively addressing a memory location in C). To get started, I > setup the GEM5 in SE with util/tlm, in which 512MB memory is modelled > in TLM. I am trying to access the memory location in the TLM through > GEM5, but I don't know how as it is not being treated as physical memory by > GEM5. > > Can someone help or has any idea, as how to have some > accelerator/memory in TLM and access it via a C program in GEM5 ? > > Regards > Yasir > ESL, EPFL > > > > > > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev -- Dipl.-Ing. Christian Menard Research Assistant TU Dresden Faculty of Computer Science Chair for Compiler Construction 01062 Dresden Phone: +49 351 463-42441 e-Mail: christian.men...@tu-dresden.de _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
