Sean Wilson has uploaded this change for review. (
https://gem5-review.googlesource.com/3925
Change subject: cpu/minor: Remove extraneous access specifiers
......................................................................
cpu/minor: Remove extraneous access specifiers
Change-Id: I0dc05dd13ad87fa4b747e8a81a72d8b94fb32b81
Signed-off-by: Sean Wilson <[email protected]>
---
M src/cpu/minor/lsq.hh
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index d4973f5..0b7edd4 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -65,7 +65,6 @@
MinorCPU &cpu;
Execute &execute;
- protected:
/** State of memory access for head access. */
enum MemoryState
{
@@ -194,7 +193,6 @@
virtual ~LSQRequest();
- public:
/** Make a packet to use with the memory transaction */
void makePacket();
@@ -297,7 +295,6 @@
* LSQRequest::packet */
void retireResponse(PacketPtr packet_) { }
- public:
SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
/* Say this is a load, not actually relevant */
LSQRequest(port_, inst_, true, NULL, 0)
@@ -322,7 +319,6 @@
public:
bool isBarrier() { return true; }
- public:
BarrierDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
SpecialDataRequest(port_, inst_)
{ state = Complete; }
@@ -364,7 +360,6 @@
* LSQRequest::packet */
void retireResponse(PacketPtr packet_);
- public:
SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_,
bool isLoad_, PacketDataPtr data_ = NULL, uint64_t *res_ =
NULL) :
LSQRequest(port_, inst_, isLoad_, data_, res_),
@@ -378,7 +373,7 @@
protected:
/** Event to step between translations */
EventFunctionWrapper translationEvent;
- protected:
+
/** Number of fragments this request is split into */
unsigned int numFragments;
@@ -404,7 +399,6 @@
/** Packets matching fragmentRequests to issue fragments to memory
*/
std::vector<Packet *> fragmentPackets;
- protected:
/** TLB response interface */
void finish(const Fault &fault_, RequestPtr request_,
ThreadContext *tc, BaseTLB::Mode mode);
@@ -416,7 +410,6 @@
~SplitDataRequest();
- public:
/** Make all the Requests for this transfer's fragments so that
those
* requests can be sent for address translation */
void makeFragmentRequests();
@@ -466,7 +459,6 @@
/** Maximum number of stores that can be issued per cycle */
const unsigned int storeLimitPerCycle;
- public:
/** Queue of store requests on their way to memory */
std::deque<LSQRequestPtr> slots;
@@ -474,12 +466,10 @@
* memory access */
unsigned int numUnissuedAccesses;
- public:
StoreBuffer(std::string name_, LSQ &lsq_,
unsigned int store_buffer_size,
unsigned int store_limit_per_cycle);
- public:
/** Can a new request be inserted into the queue? */
bool canInsert() const;
@@ -536,7 +526,6 @@
/** Memory system access width (and snap) in bytes */
const unsigned int lineWidth;
- public:
/** The LSQ consists of three queues: requests, transfers and the
* store buffer storeBuffer. */
@@ -607,7 +596,6 @@
/** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
Addr cacheBlockMask;
- protected:
/** Try and issue a memory access for a translated request at the
* head of the requests queue. Also tries to move the request
* between queues */
@@ -640,7 +628,6 @@
virtual ~LSQ();
- public:
/** Step checks the queues to see if their are issuable transfers
* which were not otherwise picked up by tests at the end of other
* events.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0dc05dd13ad87fa4b747e8a81a72d8b94fb32b81
Gerrit-Change-Number: 3925
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Wilson <[email protected]>
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