Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/4203
to review the following change.
Change subject: config, arm: SE configuration for the ARM starter kit
......................................................................
config, arm: SE configuration for the ARM starter kit
Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa <[email protected]>
Signed-off-by: Andreas Sandberg <[email protected]>
---
A configs/example/arm/starter_se.py
1 file changed, 201 insertions(+), 0 deletions(-)
diff --git a/configs/example/arm/starter_se.py
b/configs/example/arm/starter_se.py
new file mode 100644
index 0000000..ff0c94c
--- /dev/null
+++ b/configs/example/arm/starter_se.py
@@ -0,0 +1,201 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+# Chuan Zhu
+# Gabor Dozsa
+#
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+import shlex
+
+m5.util.addToPath('../..')
+
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any
of
+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+ "atomic" : ( AtomicSimpleCPU, None, None, None, None),
+ "minor" : (MinorCPU,
+ devices.L1I, devices.L1D,
+ devices.WalkCache,
+ devices.L2),
+ "hpi" : ( HPI.HPI,
+ HPI.HPI_ICache, HPI.HPI_DCache,
+ HPI.HPI_WalkCache,
+ HPI.HPI_L2)
+}
+
+
+def addOptions(parser):
+ parser.add_argument("commands_to_run", metavar="command(s)", nargs='*',
+ help="Command(s) to run")
+ parser.add_argument("--cpu", type=str, choices=cpu_types.keys(),
+ default="atomic",
+ help="CPU model to use")
+ parser.add_argument("--cpu-freq", type=str, default="4GHz")
+ parser.add_argument("--num-cores", type=int, default=1,
+ help="Number of CPU cores")
+ parser.add_argument("--mem-type", default="DDR3_1600_8x8",
+ choices=MemConfig.mem_names(),
+ help = "type of memory to use")
+ parser.add_argument("--mem-channels", type=int, default=2,
+ help = "number of memory channels")
+ parser.add_argument("--mem-ranks", type=int, default=None,
+ help = "number of memory ranks per channel")
+ parser.add_argument("--mem-size", action="store", type=str,
+ default="2GB",
+ help="Specify the physical memory size")
+
+ return parser
+
+
+def get_processes(cmd):
+ """Interprets commands to run and returns a list of processes"""
+
+ multiprocesses = []
+ for idx, c in enumerate(cmd):
+ process = Process(pid=100+idx)
+ process.cmd = shlex.split(c)
+ print "info: %d. command and arguments:" % (idx+1), process.cmd
+ process.executable = process.cmd[0]
+ process.cwd = os.getcwd()
+ multiprocesses.append(process)
+
+ return multiprocesses
+
+
+class SimpleSystem(System):
+ '''
+ Example system class for syscall emulation mode
+ '''
+ cache_line_size = 64
+
+ def __init__(self, **kwargs):
+ super(SimpleSystem, self).__init__(**kwargs)
+
+ self.voltage_domain = VoltageDomain(voltage="3.3V")
+ self.clk_domain = SrcClockDomain(clock="1GHz")
+ self.cpu_voltage_domain = VoltageDomain(voltage="1.2V")
+ self.cpu_clk_domain = SrcClockDomain(clock="4GHz")
+
+ self.membus = SystemXBar()
+ self._num_cpus = 0
+ self._clusters = []
+
+ def numCpuClusters(self):
+ return len(self._clusters)
+
+ def addCpuCluster(self, cpu_cluster, num_cpus):
+ assert cpu_cluster not in self._clusters
+ assert num_cpus > 0
+ self._clusters.append(cpu_cluster)
+ self._num_cpus += num_cpus
+
+ def numCpus(self):
+ return self._num_cpus
+
+ def connect(self, mem_size):
+ self.mem_ranges = [ AddrRange(start=0, size=mem_size) ]
+
+ self.system_port = self.membus.slave
+
+ self.clk_domain.voltage_domain=self.voltage_domain
+ self.cpu_clk_domain.voltage_domain=self.cpu_voltage_domain
+
+
+def create(args):
+ ''' Create and configure the system object. '''
+
+ cpu_class = cpu_types[args.cpu][0]
+ mem_mode = cpu_class.memory_mode()
+
+ system = SimpleSystem(mem_mode=mem_mode)
+ system.cpu_clk_domain.clock = args.cpu_freq
+ system.connect(args.mem_size)
+ MemConfig.config_mem(args, system)
+
+ # add CPUs to the system
+ system.cpu_cluster = devices.CpuCluster(system,
+ args.num_cores,
+ args.cpu_freq, "1.2V",
+ *cpu_types[args.cpu])
+
+ for cluster in system._clusters:
+ # Only simulate caches when using a timing CPU (e.g. HPI model)
+ if mem_mode == "timing":
+ cluster.addL1()
+ cluster.addL2(cluster.clk_domain)
+ cluster.connectMemSide(system.membus)
+
+ # Create processes
+ processes = get_processes(args.commands_to_run)
+ if len(processes) != args.num_cores:
+ print "Error: Cannot map %d command(s) onto %d "\
+ "CPU(s)" % (len(processes), args.num_cores)
+ sys.exit(1)
+ for cpu, workload in zip(system.cpu_cluster.cpus, processes):
+ cpu.workload = workload
+
+ return system
+
+
+def main():
+ parser = argparse.ArgumentParser()
+ addOptions(parser)
+ args = parser.parse_args()
+
+ root = Root(full_system=False)
+ root.system = create(args)
+
+ m5.instantiate()
+ event = m5.simulate()
+ print event.getCause(), " @ ", m5.curTick()
+ sys.exit(event.getCode())
+
+
+if __name__ == "__m5_main__":
+ main()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Gerrit-Change-Number: 4203
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
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