Hi folks. I notice that there's a fair bit of code in MemConfig.py which sets up a bank of memory objects to interleave memory accesses among themselves and collectively act as a single memory. This seems like something which should be bound up into a wrapping object, perhaps a RamBank SimObject, which would abstract the complexity of setting up the interleaving. There could be a specialized DramBank object which would help get rid of the ugly issubclass() in create_mem_ctrl function.
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