Xiaoyu Ma has uploaded this change for review. (
https://gem5-review.googlesource.com/4680
Change subject: Add a LPDDR4 model (2133MHz, 4267MT/s, 2X16 configuration)
......................................................................
Add a LPDDR4 model (2133MHz, 4267MT/s, 2X16 configuration)
Change-Id: I3c34ff413df268d3444d36b780ca89ce5719d93a
Signed-off-by: Xiaoyu Ma <[email protected]>
---
M src/mem/DRAMCtrl.py
1 file changed, 103 insertions(+), 0 deletions(-)
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index d1c5daf..4508f24 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -1183,3 +1183,106 @@
# self refresh exit time
tXS = '65ns'
+
+# A single LPDDR4 x32 interface (one command/address bus), with
+# default timings based on LPDDR4-2133 in a 2x16 configuration.
+class LPDDR4_4267_2x16(DRAMCtrl):
+ # No DLL for LPDDR4
+ dll = False
+
+ # size of device, arbitrary
+ device_size = '1024MB'
+
+ # Actual device has two x16 channels. For GEM5, treat them as
+ # separate devices.
+ device_bus_width = 16
+
+ # LPDDR4 supports BL16 and BL32, or both, but we will assume a MC that
+ # supports only 16
+ burst_length = 16
+
+ # Each device has a page (row buffer) size of 2KB
+ device_rowbuffer_size = '2kB'
+
+ # 2x16 configuration
+ devices_per_rank = 2
+
+ # Use two ranks
+ ranks_per_channel = 2
+
+ # LPDDR4 has 8 banks
+ banks_per_rank = 8
+
+ # 1866 MHz
+ tCK = '0.467ns'
+
+ # Greater of 4 CK or 18 ns
+ tRCD = '18ns'
+
+ # 24 CK read latency, 12 CK write latency
+ # This is a guess. Current JEDEC spec does not specify
+ tCL = '12ns'
+
+ # Greater of 3 CK or 42 ns
+ tRAS = '42ns'
+
+ # Greater of 4 CK or 18 ns
+ tWR = '18ns'
+
+ # Greater of 8 CK or 7.5 ns
+ tRTP = '7.5ns'
+
+ # Pre-charge one bank 18 ns (all banks 21 ns)
+ tRP = '18ns'
+
+ # 16 beats translates to 8 clocks
+ tBURST = '3.736ns'
+
+ # LPDDR4, 8Gb
+ tRFC = '180ns'
+ tREFI = '3.904us'
+
+ # Greater of 8 CK or 10 ns
+ tWTR = '10ns'
+
+ # Default same rank rd-to-wr bus turnaround to 2 CK
+ tRTW = '0.934ns'
+
+ # Default different rank bus delay to 2 CK
+ tCS = '0.934ns'
+
+ # Activate to activate, greater of 8 CK or 10 ns
+ tRRD = '10ns'
+
+ # Irrespective of size, tXAW is 40 ns
+ tXAW = '40ns'
+ activation_limit = 4
+
+ # Time to exit self-refresh mode with locked DLL, tRFC + 7.5 ns
+ tXSDLL = '187.5ns'
+
+ # Power modeling parameters
+ IDD0 = '12mA'
+ IDD02 = '82mA'
+ IDD2P0 = '2.4mA'
+ IDD2P02 = '5.5mA'
+ IDD2P1 = '2.4mA'
+ IDD2P12 = '5.5mA'
+ IDD2N = '4.5mA'
+ IDD2N2 = '31mA'
+ IDD3P0 = '3.5mA'
+ IDD3P02 = '15mA'
+ IDD3P1 = '3.5mA'
+ IDD3P12 = '15mA'
+ IDD3N = '4.5mA'
+ IDD3N2 = '45mA'
+ IDD4R = '5.5mA'
+ IDD4R2 = '300mA'
+ IDD4W = '5mA'
+ IDD4W2 = '245mA'
+ IDD5 = '70mA'
+ IDD52 = '220mA'
+ IDD6 = '1.3mA'
+ IDD62 = '2mA'
+ VDD = '1.8V'
+ VDD2 = '1.1V'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3c34ff413df268d3444d36b780ca89ce5719d93a
Gerrit-Change-Number: 4680
Gerrit-PatchSet: 1
Gerrit-Owner: Xiaoyu Ma <[email protected]>
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