Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/5732
Change subject: cpu: Add missing instruction class stats
......................................................................
cpu: Add missing instruction class stats
This patch adds the SIMD instruction class and adds it to
Minor and O3. It also adds missing stats in the Minor model.
Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/pipeline.cc
M src/cpu/minor/pipeline.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/static_inst.hh
8 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index d7d32e6..0247fd5 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -546,6 +546,7 @@
bool isLastMicroop() const { return staticInst->isLastMicroop(); }
bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
bool isMicroBranch() const { return staticInst->isMicroBranch(); }
+ bool isSimd() const { return staticInst->isSimd(); }
/** Temporarily sets this instruction as a serialize before
instruction. */
void setSerializeBefore() { status.set(SerializeBefore); }
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 986f1f2..5dc255e 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014,2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -415,6 +415,17 @@
dyn_inst->pc = fetch_info.pc;
DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);
+ // Collect some basic inst class stats
+ if (decoded_inst->isLoad())
+ loadInstructions++;
+ else if (decoded_inst->isStore())
+ storeInstructions++;
+ else if (decoded_inst->isSimd())
+ simdInstructions++;
+ else if (decoded_inst->isFloating())
+ fpInstructions++;
+ else if (decoded_inst->isInteger())
+ intInstructions++;
DPRINTF(Fetch, "Instruction extracted from line %s"
" lineWidth: %d output_index: %d inputIndex: %d"
@@ -594,6 +605,37 @@
}
void
+Fetch2::regStats()
+{
+ using namespace Stats;
+
+ intInstructions
+ .name(name() + ".int_instructions")
+ .desc("Number of integer instructions successfully decoded")
+ .flags(total);
+
+ fpInstructions
+ .name(name() + ".fp_instructions")
+ .desc("Number of floating point instructions successfully decoded")
+ .flags(total);
+
+ simdInstructions
+ .name(name() + ".simd_instructions")
+ .desc("Number of SIMD instructions successfully decoded")
+ .flags(total);
+
+ loadInstructions
+ .name(name() + ".load_instructions")
+ .desc("Number of memory load instructions successfully decoded")
+ .flags(total);
+
+ storeInstructions
+ .name(name() + ".store_instructions")
+ .desc("Number of memory store instructions successfully decoded")
+ .flags(total);
+}
+
+void
Fetch2::minorTrace() const
{
std::ostringstream data;
diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh
index 33c683b..1025ca0 100644
--- a/src/cpu/minor/fetch2.hh
+++ b/src/cpu/minor/fetch2.hh
@@ -165,6 +165,13 @@
std::vector<Fetch2ThreadInfo> fetchInfo;
ThreadID threadPriority;
+ /** Stats */
+ Stats::Scalar intInstructions;
+ Stats::Scalar fpInstructions;
+ Stats::Scalar simdInstructions;
+ Stats::Scalar loadInstructions;
+ Stats::Scalar storeInstructions;
+
protected:
/** Get a piece of data to work on from the inputBuffer, or 0 if there
* is no data. */
@@ -206,6 +213,8 @@
void minorTrace() const;
+ void regStats();
+
/** Is this stage drained? For Fetch2, draining is initiated by
* Execute halting Fetch1 causing Fetch2 to naturally drain.
* Branch predictions are ignored by Fetch1 during halt */
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 08dc3db..b5659ac 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -106,6 +106,14 @@
}
void
+Pipeline::regStats()
+{
+ Ticked::regStats();
+
+ fetch2.regStats();
+}
+
+void
Pipeline::minorTrace() const
{
fetch1.minorTrace();
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index 9b6ca0d..5748232 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -133,6 +133,9 @@
void minorTrace() const;
+ /** Stats registering */
+ void regStats();
+
/** Functions below here are BaseCPU operations passed on to pipeline
* stages */
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 64f8aa1..6922b22 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -551,6 +551,7 @@
Stats::Scalar intAluAccesses;
Stats::Scalar fpAluAccesses;
Stats::Scalar vecAluAccesses;
+ Stats::Scalar simdAluAccesses;
};
#endif //__CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 3da72fd..12d2d56 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2014 ARM Limited
+ * Copyright (c) 2011-2014,2016 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -379,6 +379,11 @@
.desc("Number of floating point alu accesses")
.flags(total);
+ simdAluAccesses
+ .name(name() + ".simd_alu_accesses")
+ .desc("Number of SIMD alu accesses")
+ .flags(total);
+
}
template <class Impl>
@@ -830,13 +835,17 @@
if (op_class != No_OpClass) {
idx = fuPool->getUnit(op_class);
+
if (issuing_inst->isFloating()) {
fpAluAccesses++;
+ } else if (issuing_inst->isSimd()) {
+ simdAluAccesses++;
} else if (issuing_inst->isVector()) {
vecAluAccesses++;
} else {
intAluAccesses++;
}
+
if (idx > FUPool::NoFreeFU) {
op_latency = fuPool->getOpLatency(op_class);
}
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 883c532..e5adb3d 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2016 ARM Limited
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -183,6 +184,20 @@
bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
//This flag doesn't do anything yet
bool isMicroBranch() const { return flags[IsMicroBranch]; }
+ bool isSimd() const {
+ return (
+ _opClass == SimdAddOp || _opClass == SimdAddAccOp ||
+ _opClass == SimdAluOp || _opClass == SimdCmpOp ||
+ _opClass == SimdCvtOp || _opClass == SimdMiscOp ||
+ _opClass == SimdMultOp || _opClass == SimdMultAccOp ||
+ _opClass == SimdShiftOp || _opClass == SimdShiftAccOp ||
+ _opClass == SimdSqrtOp || _opClass == SimdFloatAddOp ||
+ _opClass == SimdFloatAluOp || _opClass == SimdFloatCmpOp ||
+ _opClass == SimdFloatCvtOp || _opClass == SimdFloatDivOp ||
+ _opClass == SimdFloatMiscOp || _opClass == SimdFloatMultOp ||
+ _opClass == SimdFloatMultAccOp || _opClass == SimdFloatSqrtOp
+ );
+ }
//@}
void setFirstMicroop() { flags[IsFirstMicroop] = true; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I811b552989caf3601ac65a128dbee6b7bb405d7f
Gerrit-Change-Number: 5732
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
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