Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6023
Change subject: arch-riscv: Move unknown out of ISA description
......................................................................
arch-riscv: Move unknown out of ISA description
This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts. Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.
Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.cc
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 61 insertions(+), 42 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index fe90280..3da7ba3 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,4 +2,5 @@
if env['TARGET_ISA'] == 'riscv':
Source('standard.cc')
- Source('static_inst.cc')
\ No newline at end of file
+ Source('static_inst.cc')
+ Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh
b/src/arch/riscv/insts/bitfields.hh
index 45744e0..d664822 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@
#define CSRIMM bits(machInst, 19, 15)
#define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE bits(machInst, 6, 0)
#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.cc
b/src/arch/riscv/insts/unknown.cc
new file mode 100644
index 0000000..aaec865
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.cc
@@ -0,0 +1,17 @@
+#include "arch/riscv/insts/unknown.hh"
+
+#include <string>
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ return csprintf("unknown opcode 0x%02x", OPCODE);
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.hh
b/src/arch/riscv/insts/unknown.hh
new file mode 100644
index 0000000..0540371
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,40 @@
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include <memory>
+#include <string>
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode. This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+ public:
+ /// Constructor
+ Unknown(MachInst _machInst)
+ : RiscvStaticInst("unknown", _machInst, No_OpClass)
+ {
+ flags[IsNonSpeculative] = true;
+ }
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const
+ {
+ return std::make_shared<UnknownInstFault>();
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/unknown.isa
b/src/arch/riscv/isa/formats/unknown.isa
index b6d7649..7c2317f 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
//
// Unknown instructions
//
-
-output header {{
- /**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode. This is a leaf class.
- */
- class Unknown : public RiscvStaticInst
- {
- public:
- /// Constructor
- Unknown(MachInst _machInst)
- : RiscvStaticInst("unknown", _machInst, No_OpClass)
- {
- flags[IsNonSpeculative] = true;
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const;
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string
- Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("unknown opcode 0x%02x", OPCODE);
- }
-}};
-
-output exec {{
- Fault
- Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
- {
- Fault fault = std::make_shared<UnknownInstFault>();
- return fault;
- }
-}};
-
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index dfd0f37..cd43996 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/insts/unknown.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Gerrit-Change-Number: 6023
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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