Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/6024
to look at the new patch set (#5).
Change subject: arch-riscv: Move parts of mem insts out of ISA
......................................................................
arch-riscv: Move parts of mem insts out of ISA
This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts. It also
simplifies the definitions of load and store instructions by giving
them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/mem.cc
A src/arch/riscv/insts/mem.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 194 insertions(+), 115 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Gerrit-Change-Number: 6024
Gerrit-PatchSet: 5
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-CC: Gabe Black <gabebl...@google.com>
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