Hi Sam, The way *I* would do this (though it may not be the best way) is to do what you suggest, precompute the cpuid value in python and set that as a parameter on the System object (maybe the CPU? Can different cores return different cpuid values?).
You should be able to access all of this information from Python. The hardest part is trying to make the code general. For instance, there is no way for you as the API writer will know what the gem5 user will name their caches. Usually it's icache/dcache, but there's nothing in gem5 to enforce those names (for good reason!). My initial thought is to add a python function to the System which takes "caches" as parameters. "Caches" in the sense of Python's duck typing so you could pass either a Cache object or a RubyCache object (they both have parameters named "size" and "assoc" so they should be interchangeable here). This function can compute the needed value for the cpuid. If you think it's more appropriate to have the cpuid a parameter of the CPU, then maybe the computeCpuid function should be a helper function somewhere else (I'm not sure where would be best. I suppose BaseCPU would make sense.). Please submit a patch when you do implement this! :) Cheers, Jason ----------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://faculty.engineering.ucdavis.edu/lowepower/ On Tue, Dec 12, 2017 at 9:07 PM Sam Xi <liku...@fas.harvard.edu> wrote: > Hi, > > I am trying to implement another part of the cpuid instruction, namely leaf > 4, which returns deterministic cache parameters of the system (size, > associativity, etc). However, I'm a bit stumped as to how I can actually > access this information. There doesn't seem to be any way to get a pointer > to a Cache object from the CPU or the System. The most I've been able to > find is getting a handle to the master port for either the icache or the > dcache, but even then there's no way to get a handle to the owner of the > corresponding slave port. It seems that the only bird's eye view of the > system is available in Python. So if this is all true, then would the best > way to implement this to be precomputing all the register outputs in python > and setting them appropriately in the CPU objects as the caches are > instantiated? > > Thanks, > Sam > -- > Thanks, > > Sam Xi > Harvard University > Computer Science, Ph.D. Candidate > http://www.samxi.org > _______________________________________________ > gem5-dev mailing list > gem5-dev@gem5.org > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
