Tuan Ta has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6904 )
Change subject: arch-riscv,sim: Support clone syscall in RISC-V
......................................................................
arch-riscv,sim: Support clone syscall in RISC-V
(1) This patch sets a correct order of clone syscall's arguments for
RISC-V. Linux kernel 4.15 uses CLONE_BACKWARDS flag by default for
RISC-V. The flag in the Linux kernel defines the list of clone syscall's
arguments in the following order:
clone_flags (flags)
newsp (newStack)
parent_tidptr (ptidPtr)
tls (tlsPtr)
child_tidptr (ctidPtr)
Code reference:
https://github.com/riscv/riscv-linux/blob/master/kernel/fork.c
https://github.com/riscv/riscv-linux/blob/master/arch/riscv/Kconfig
(2) This patch copies a parent thread's register values to its child
thread in clone syscall.
Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf
Reviewed-on: https://gem5-review.googlesource.com/6904
Maintainer: Brandon Potter <[email protected]>
Reviewed-by: Alec Roelke <[email protected]>
---
M src/sim/syscall_emul.hh
1 file changed, 13 insertions(+), 1 deletion(-)
Approvals:
Alec Roelke: Looks good to me, approved
Brandon Potter: Looks good to me, approved
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 2ffd6d6..ef61299 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1241,11 +1241,23 @@
cloneFunc(SyscallDesc *desc, int callnum, Process *p, ThreadContext *tc)
{
int index = 0;
+
TheISA::IntReg flags = p->getSyscallArg(tc, index);
TheISA::IntReg newStack = p->getSyscallArg(tc, index);
Addr ptidPtr = p->getSyscallArg(tc, index);
+
+#if THE_ISA == RISCV_ISA
+ /**
+ * Linux kernel 4.15 sets CLONE_BACKWARDS flag for RISC-V.
+ * The flag defines the list of clone() arguments in the following
+ * order: flags -> newStack -> ptidPtr -> tlsPtr -> ctidPtr
+ */
+ Addr tlsPtr M5_VAR_USED = p->getSyscallArg(tc, index);
+ Addr ctidPtr = p->getSyscallArg(tc, index);
+#else
Addr ctidPtr = p->getSyscallArg(tc, index);
Addr tlsPtr M5_VAR_USED = p->getSyscallArg(tc, index);
+#endif
if (((flags & OS::TGT_CLONE_SIGHAND)&& !(flags & OS::TGT_CLONE_VM)) ||
((flags & OS::TGT_CLONE_THREAD) && !(flags &
OS::TGT_CLONE_SIGHAND)) ||
@@ -1340,7 +1352,7 @@
ctc->setMiscReg(TheISA::MISCREG_ASI, TheISA::ASI_PRIMARY);
for (int y = 8; y < 32; y++)
ctc->setIntReg(y, tc->readIntReg(y));
-#elif THE_ISA == ARM_ISA or THE_ISA == X86_ISA
+#elif THE_ISA == ARM_ISA or THE_ISA == X86_ISA or THE_ISA == RISCV_ISA
TheISA::copyRegs(tc, ctc);
#endif
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf
Gerrit-Change-Number: 6904
Gerrit-PatchSet: 5
Gerrit-Owner: Tuan Ta <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Brandon Potter <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
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