Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7349 )
Change subject: cpu: Make the CPU's TLB parameter a BaseTLB.
......................................................................
cpu: Make the CPU's TLB parameter a BaseTLB.
This is instead of the architecture specific version.
Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/cpu/BaseCPU.py
1 file changed, 10 insertions(+), 21 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index d174f27..c100f0e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -57,37 +57,38 @@
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
- from AlphaTLB import AlphaDTB, AlphaITB
+ from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
from AlphaInterrupts import AlphaInterrupts
from AlphaISA import AlphaISA
default_isa_class = AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
- from SparcTLB import SparcTLB
+ from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
from SparcInterrupts import SparcInterrupts
from SparcISA import SparcISA
default_isa_class = SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
- from X86TLB import X86TLB
+ from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
from X86LocalApic import X86LocalApic
from X86ISA import X86ISA
default_isa_class = X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
- from MipsTLB import MipsTLB
+ from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
from MipsInterrupts import MipsInterrupts
from MipsISA import MipsISA
default_isa_class = MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
- from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
+ from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
+ from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
from ArmInterrupts import ArmInterrupts
from ArmISA import ArmISA
default_isa_class = ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
- from PowerTLB import PowerTLB
+ from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
from PowerInterrupts import PowerInterrupts
from PowerISA import PowerISA
default_isa_class = PowerISA
elif buildEnv['TARGET_ISA'] == 'riscv':
- from RiscvTLB import RiscvTLB
+ from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
from RiscvInterrupts import RiscvInterrupts
from RiscvISA import RiscvISA
default_isa_class = RiscvISA
@@ -162,32 +163,24 @@
workload = VectorParam.Process([], "processes to run")
+ dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
+ itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
if buildEnv['TARGET_ISA'] == 'sparc':
- dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
- itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
interrupts = VectorParam.SparcInterrupts(
[], "Interrupt Controller")
isa = VectorParam.SparcISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'alpha':
- dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
- itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
interrupts = VectorParam.AlphaInterrupts(
[], "Interrupt Controller")
isa = VectorParam.AlphaISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'x86':
- dtb = Param.X86TLB(X86TLB(), "Data TLB")
- itb = Param.X86TLB(X86TLB(), "Instruction TLB")
interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
isa = VectorParam.X86ISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'mips':
- dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
- itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
interrupts = VectorParam.MipsInterrupts(
[], "Interrupt Controller")
isa = VectorParam.MipsISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'arm':
- dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
- itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
interrupts = VectorParam.ArmInterrupts(
@@ -195,14 +188,10 @@
isa = VectorParam.ArmISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
- dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
- itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
interrupts = VectorParam.PowerInterrupts(
[], "Interrupt Controller")
isa = VectorParam.PowerISA([], "ISA instance")
elif buildEnv['TARGET_ISA'] == 'riscv':
- dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
- itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
interrupts = VectorParam.RiscvInterrupts(
[], "Interrupt Controller")
isa = VectorParam.RiscvISA([], "ISA instance")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Gerrit-Change-Number: 7349
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Alexandru Duțu <alexandru.d...@amd.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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