Hi all, I have a student who is interested in extending the RISC-V support in gem5 as part of his Master's thesis. The focus would be to enable FS support (at least for bare-metal applications, not necessarily for Linux) and to define an interface for the addition of user defined custom instructions. The goal would be to simulate a full embedded system with a user defined custom instruction set.
I know that some people here are working on RISC-V and I would like to sync up before we actually start our work. Is somebody already working in this direction? Are you aware of any problems that might be in the way? Do you have an idea on what would be a good way to implement custom instructions for RISC-V? Cheers, Christian -- Dipl.-Ing. Christian Menard Research Assistant TU Dresden Faculty of Computer Science Chair for Compiler Construction 01062 Dresden Phone: +49 351 463-42441 e-Mail: [email protected] _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
