Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/7982
to review the following change.
Change subject: arch-arm: Change function name for banked miscregs
......................................................................
arch-arm: Change function name for banked miscregs
This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.
Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
7 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 106ec32..b5cf58f 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -880,7 +880,7 @@
// Get the index of the banked version of SCTLR:
// SCTLR_s or SCTLR_ns.
- auto banked_sctlr = flattenMiscRegNsBanked(
+ auto banked_sctlr = snsBankedIndex(
MISCREG_SCTLR, tc, !inSecureState(tc));
// SCTLR.SED bit is enabling/disabling the ue of SETEND
instruction.
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 23962b0..13da2bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -872,7 +872,7 @@
exec_output += PredOpExecute.subst(mcr14Iop)
mrc15code = '''
- int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+ int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatOp1)).index();
@@ -904,7 +904,7 @@
mcr15code = '''
- int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+ int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatDest)).index();
@@ -937,7 +937,7 @@
mrrc15code = '''
- int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+ int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatOp1)).index();
@@ -968,7 +968,7 @@
mcrr15code = '''
- int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+ int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatDest)).index();
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index babf0ac..3daba57 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -102,11 +102,11 @@
xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
'''
cntrlNsBankedWrite = '''
- xc->setMiscReg(flattenMiscRegNsBanked(dest,
xc->tcBase()), %(final_val)s)
+ xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
'''
cntrlNsBankedRead = '''
- xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
+ xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
'''
#PCState operands need to have a sorting index (the number at the end)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18..a9031fe 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -815,14 +815,14 @@
}
int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
{
SCR scr = tc->readMiscReg(MISCREG_SCR);
- return flattenMiscRegNsBanked(reg, tc, scr.ns);
+ return snsBankedIndex(reg, tc, scr.ns);
}
int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 779ead7..8cfa013 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1891,14 +1891,14 @@
// Uses just the scr.ns bit to pre flatten the misc regs. This is
useful
// for MCR/MRC instructions
int
- flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
+ snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
// Flattens a misc reg index using the specified security state. This
is
// used for opperations (eg address translations) where the security
// state of the register access may differ from the current state of
the
// processor
int
- flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
+ snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
// Takes a misc reg index and returns the root reg if its one of a set
of
// banked registers
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 88f6eae..428556b 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -281,9 +281,9 @@
}
currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
} else {
- currState->sctlr =
currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_SCTLR, currState->tc, !currState->isSecure));
- currState->ttbcr =
currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_TTBCR, currState->tc, !currState->isSecure));
currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR);
currState->hcr = currState->tc->readMiscReg(MISCREG_HCR);
@@ -484,7 +484,7 @@
ArmFault::TranslationLL + L1, isStage2,
ArmFault::VmsaTran);
}
- ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ ttbr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_TTBR0, currState->tc, !currState->isSecure));
} else {
DPRINTF(TLB, " - Selecting TTBR1\n");
@@ -503,7 +503,7 @@
ArmFault::TranslationLL + L1, isStage2,
ArmFault::VmsaTran);
}
- ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ ttbr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_TTBR1, currState->tc, !currState->isSecure));
currState->ttbcr.n = 0;
}
@@ -616,7 +616,7 @@
isStage2,
ArmFault::LpaeTran);
}
- ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ ttbr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_TTBR0, currState->tc, !currState->isSecure));
tsz = currState->ttbcr.t0sz;
if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB
@@ -640,7 +640,7 @@
isStage2,
ArmFault::LpaeTran);
}
- ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+ ttbr = currState->tc->readMiscReg(snsBankedIndex(
MISCREG_TTBR1, currState->tc, !currState->isSecure));
tsz = currState->ttbcr.t1sz;
if (ttbr1_min >= (1ULL << 31) + (1ULL << 30)) // Lower limit
= 3 GB
@@ -1064,9 +1064,9 @@
}
} else {
assert(tc);
- PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR,
+ PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR,
currState->tc, !currState->isSecure));
- NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR,
+ NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR,
currState->tc, !currState->isSecure));
DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
@@ -1228,8 +1228,8 @@
// LPAE always uses remapping of memory attributes, irrespective
of the
// value of SCTLR.TRE
MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
- int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc,
- !currState->isSecure);
+ int reg_as_int = snsBankedIndex(reg, currState->tc,
+ !currState->isSecure);
uint32_t mair = currState->tc->readMiscReg(reg_as_int);
attr = (mair >> (8 * (attrIndx % 4))) & 0xff;
uint8_t attr_7_4 = bits(attr, 7, 4);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d3f44c3..3aebe3d 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1328,28 +1328,28 @@
stage2Req = false;
}
} else { // AArch32
- sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
+ sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
!isSecure));
- ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc,
+ ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
!isSecure));
scr = tc->readMiscReg(MISCREG_SCR);
isPriv = cpsr.mode != MODE_USER;
if (longDescFormatInUse(tc)) {
uint64_t ttbr_asid = tc->readMiscReg(
- flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1
- : MISCREG_TTBR0,
+ snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 :
+ MISCREG_TTBR0,
tc, !isSecure));
asid = bits(ttbr_asid, 55, 48);
} else { // Short-descriptor translation table format in use
- CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked(
+ CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex(
MISCREG_CONTEXTIDR, tc,!isSecure));
asid = context_id.asid;
}
- prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc,
+ prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc,
!isSecure));
- nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc,
+ nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc,
!isSecure));
- dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc,
+ dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc,
!isSecure));
hcr = tc->readMiscReg(MISCREG_HCR);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Gerrit-Change-Number: 7982
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
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