Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/9043
Change subject: x86: Implement the RDTSCP instruction.
......................................................................
x86: Implement the RDTSCP instruction.
This is very similar to RDTSC, except that it requires all younger
instructions to retire before it completes, and it writes the TSC_AUX
MSR into ECX. I've added an mfence as an iniitial microop to ensure
that memory accesses complete before RDTSCP runs, and added an rdval
microop at the end to read the TSC_AUX value into ECX.
Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/msrs.py
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index aa60e4c..761e838 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -133,7 +133,7 @@
0x7: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: Inst::SWAPGS();
- 0x1: rdtscp();
+ 0x1: Inst::RDTSCP();
default: Inst::UD2();
}
default: Inst::INVLPG(M);
diff --git a/src/arch/x86/isa/insts/system/msrs.py
b/src/arch/x86/isa/insts/system/msrs.py
index fe9c5b2..b79b6db 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -66,4 +66,15 @@
srli t1, t1, 32, dataSize=8
mov rdx, rdx, t1, dataSize=4
};
+
+def macroop RDTSCP
+{
+ .serialize_before
+ mfence
+ rdtsc t1
+ mov rax, rax, t1, dataSize=4
+ srli t1, t1, 32, dataSize=8
+ mov rdx, rdx, t1, dataSize=4
+ rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4
+};
'''
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
Gerrit-Change-Number: 9043
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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