Hello Brandon Potter,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/8181
to look at the new patch set (#2).
Change subject: cpu: Prevent suspended TimingSimple CPUs from fetching next
instructions
......................................................................
cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.
This patch added a status check before a CPU schedule a fetch event
after a fault is handled.
Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
---
M CONTRIBUTING.md
M SConstruct
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/MemConfig.py
M configs/common/PlatformConfig.py
M configs/common/Simulation.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/se.py
M configs/learning_gem5/README
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
A configs/learning_gem5/part3/msi_caches.py
A configs/learning_gem5/part3/ruby_caches_MI_example.py
A configs/learning_gem5/part3/ruby_test.py
A configs/learning_gem5/part3/simple_ruby.py
A configs/learning_gem5/part3/test_caches.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M ext/systemc/src/sysc/qt/SConscript.sc
M site_scons/site_init.py
M site_scons/site_tools/git.py
M site_scons/site_tools/mercurial.py
M src/SConscript
M src/arch/alpha/isa/branch.isa
M src/arch/alpha/isa/fp.isa
M src/arch/alpha/isa/int.isa
M src/arch/alpha/isa/main.isa
M src/arch/alpha/isa/mem.isa
M src/arch/alpha/isa/opcdec.isa
M src/arch/alpha/isa/pal.isa
M src/arch/alpha/isa/unimp.isa
A src/arch/arm/ArmSemihosting.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/branch64.hh
M src/arch/arm/insts/data64.hh
M src/arch/arm/insts/macromem.hh
M src/arch/arm/insts/mem.hh
M src/arch/arm/insts/mem64.hh
M src/arch/arm/insts/misc.hh
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/pseudo.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/insts/vfp.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/decoder/arm.isa
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/breakpoint.isa
M src/arch/arm/isa/formats/data.isa
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/formats/mem.isa
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/isa/formats/mult.isa
M src/arch/arm/isa/formats/neon64.isa
M src/arch/arm/isa/insts/branch64.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/isa/insts/str64.isa
M src/arch/arm/isa/templates/basic.isa
M src/arch/arm/isa/templates/branch.isa
M src/arch/arm/isa/templates/branch64.isa
M src/arch/arm/isa/templates/data64.isa
M src/arch/arm/isa/templates/macromem.isa
M src/arch/arm/isa/templates/mem.isa
M src/arch/arm/isa/templates/mem64.isa
M src/arch/arm/isa/templates/misc.isa
M src/arch/arm/isa/templates/misc64.isa
M src/arch/arm/isa/templates/mult.isa
M src/arch/arm/isa/templates/neon.isa
M src/arch/arm/isa/templates/neon64.isa
M src/arch/arm/isa/templates/pred.isa
A src/arch/arm/isa/templates/semihost.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/isa/templates/vfp.isa
M src/arch/arm/isa/templates/vfp64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
A src/arch/arm/semihosting.cc
A src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
A src/arch/arm/tlbi_op.cc
A src/arch/arm/tlbi_op.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/decode_cache.cc
M src/arch/generic/decode_cache.hh
M src/arch/hsail/gen.py
M src/arch/isa_parser.py
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/mips/isa/base.isa
M src/arch/mips/isa/formats/basic.isa
M src/arch/mips/isa/formats/branch.isa
M src/arch/mips/isa/formats/control.isa
M src/arch/mips/isa/formats/fp.isa
M src/arch/mips/isa/formats/int.isa
M src/arch/mips/isa/formats/mem.isa
M src/arch/mips/isa/formats/mt.isa
M src/arch/mips/isa/formats/noop.isa
M src/arch/mips/isa/formats/tlbop.isa
M src/arch/mips/isa/formats/trap.isa
M src/arch/mips/isa/formats/unimp.isa
M src/arch/mips/isa/formats/unknown.isa
M src/arch/power/insts/branch.hh
M src/arch/power/insts/condition.hh
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.hh
M src/arch/power/insts/mem.hh
M src/arch/power/insts/misc.hh
M src/arch/power/insts/static_inst.hh
M src/arch/power/isa/formats/basic.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
M src/arch/riscv/decoder.hh
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/sparc/insts/nop.cc
M src/arch/sparc/insts/priv.hh
M src/arch/sparc/insts/static_inst.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa/formats/basic.isa
M src/arch/sparc/isa/formats/mem/basicmem.isa
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/arch/x86/decoder.cc
M src/arch/x86/decoder.hh
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
M src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
M src/arch/x86/isa/insts/system/invlpg.py
M src/arch/x86/isa/insts/system/msrs.py
M src/arch/x86/isa/insts/system/segmentation.py
M src/arch/x86/isa/macroop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/linux/process.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
M src/arch/x86/system.cc
M src/base/bitunion.hh
M src/base/bituniontest.cc
M src/base/compiler.hh
M src/base/pngwriter.cc
M src/base/statistics.hh
M src/cpu/BaseCPU.py
M src/cpu/decode_cache.hh
M src/cpu/inst_pb_trace.cc
M src/cpu/inst_pb_trace.hh
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/simple/BaseSimpleCPU.py
M src/cpu/simple/timing.cc
M src/cpu/static_inst.hh
M src/cpu/testers/rubytest/Check.cc
M src/dev/arm/RealView.py
M src/dev/mips/malta.cc
M src/dev/mips/malta_cchip.cc
M src/dev/mips/malta_io.cc
M src/dev/net/ethertap.cc
M src/dev/net/ns_gige.cc
M src/dev/serial/Terminal.py
M src/dev/serial/terminal.hh
M src/dev/sparc/dtod.cc
M src/dev/sparc/mm_disk.cc
M src/dev/sparc/t1000.cc
M src/dev/virtio/fs9p.cc
M src/gpu-compute/hsail_code.cc
M src/gpu-compute/hsail_code.hh
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/mshr.hh
M src/mem/cache/prefetch/base.hh
A src/mem/cache/replacement_policies/ReplacementPolicies.py
A src/mem/cache/replacement_policies/SConscript
C src/mem/cache/replacement_policies/base.cc
A src/mem/cache/replacement_policies/base.hh
A src/mem/cache/replacement_policies/brrip_rp.cc
A src/mem/cache/replacement_policies/brrip_rp.hh
C src/mem/cache/replacement_policies/fifo_rp.cc
C src/mem/cache/replacement_policies/fifo_rp.hh
C src/mem/cache/replacement_policies/lfu_rp.cc
C src/mem/cache/replacement_policies/lfu_rp.hh
A src/mem/cache/replacement_policies/lru_rp.cc
A src/mem/cache/replacement_policies/lru_rp.hh
A src/mem/cache/replacement_policies/mru_rp.cc
A src/mem/cache/replacement_policies/mru_rp.hh
A src/mem/cache/replacement_policies/random_rp.cc
R src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/tags/SConscript
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
D src/mem/cache/tags/lru.cc
D src/mem/cache/tags/lru.hh
D src/mem/cache/tags/random_repl.cc
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/page_table.cc
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/SConscript
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
M src/mem/slicc/main.py
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/util.py
M src/proto/inst.proto
M src/python/m5/SimObject.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/main.py
M src/python/m5/params.py
M src/python/m5/simulate.py
M src/python/m5/ticks.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/sorteddict.py
M src/python/m5/util/terminal.py
M src/sim/byteswap.hh
M src/sim/power/PowerModel.py
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/syscall_emul.hh
M src/unittest/genini.py
M tests/SConscript
M tests/configs/base_config.py
M tests/configs/checkpoint.py
M tests/configs/gpu-ruby.py
M tests/configs/switcheroo.py
M tests/long/se/70.twolf/test.py
M tests/quick/se/04.gpu/test.py
M tests/quick/se/70.twolf/test.py
M tests/run.py
A tests/test-progs/threads/bin/x86/linux/threads
A tests/test-progs/threads/src/Makefile
A tests/test-progs/threads/src/threads.cpp
M tests/testing/helpers.py
M tests/testing/results.py
M tests/tests.py
326 files changed, 9,204 insertions(+), 3,174 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Gerrit-Change-Number: 8181
Gerrit-PatchSet: 2
Gerrit-Owner: Tuan Ta <[email protected]>
Gerrit-Reviewer: Brandon Potter <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
Gerrit-MessageType: newpatchset
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