Hi Gabe, Thank you very much for your reply. Yet I think MOVNTI has been a store instruction using non-temporal hints for years. Please allow me to repeat my question in more details. In my program I called a function _mm_stream_si64(__int64 *p, __int64 a) provided by Intel to copy data from one array to another (cf. https://software.intel.com/en-us/node/524246). That function would call MOVNTI which is one of the store instructions using non-temporal hints. As mentioned in the developer manual, non-temporal store instructions "prevent non-temporal data from being written into processor caches on a store operation" (cf. Page 283 of https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf ). I added a print function to the Class Packet in ./src/mem/packet.hh. In ./src/mem/cache/cache.cc, I called that print function of Packet in Cache::recvTimingReq() function in ./src/mem/cache/cache.cc and observed that non-temporal store instructions would write data to cache. And, as requested by non-temporal store instructions, "if the memory location being written to is present in the cache hierarchy, the data in the caches is evicted." (cf Page 252 of the manual). An eviction of the data to memory was not observed also. Today I replaced the function _mm_stream_si64 with the ordinary memcpy function. I find that the two functions behave the same in terms of cache write/read with Gem5.
Best Regards, Le On Mon, Jul 9, 2018 at 7:29 PM, Gabe Black <[email protected]> wrote: > Hi Le. I just checked, and the MOVNTI instruction doesn't have any special > handling to tell it to be non-temporal. I think relatively recently there > was a flag added which lets you specify a memory operation as uncacheable. > I'm not sure if the semantics would match perfectly, but that could make > the instructions behave more like what you expect. > > Gabe > > On Fri, Jul 6, 2018 at 5:31 AM dongle <[email protected]> wrote: > > > Dear all, > > > > I run a program that calls non-temporal store instructions (e.g., movnti) > > in SE module after building build/X86/gem5.opt. Non-temporal store > > instructions should bypass CPU cache and directly store data from > register > > to memory. However, I find that they still write data to CPU cache. Could > > you check this? > > > > Best Regards, > > Le > > _______________________________________________ > > gem5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
