Giacomo Travaglini has uploaded a new patch set (#4) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13523 )
Change subject: arch-arm: Add support for first-/non-faulting loads
......................................................................
arch-arm: Add support for first-/non-faulting loads
In addition to the ISA-level changes, this changeset includes all the
necessary modifications to the various CPU models to properly handle
the new faulting behaviours.
Change-Id: I3c9e66bfee6a642570cf46980ba7e3a96a17b599
Signed-off-by: Gabor Dozsa <gabor.do...@arm.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/utils.hh
M src/mem/abstract_mem.cc
M src/mem/packet.hh
M src/mem/request.hh
M src/sim/faults.cc
M src/sim/faults.hh
33 files changed, 1,115 insertions(+), 507 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I3c9e66bfee6a642570cf46980ba7e3a96a17b599
Gerrit-Change-Number: 13523
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-Reviewer: Gabor Dozsa <gabor.do...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newpatchset
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