Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13999
to review the following change.
Change subject: arch-arm: Implement AArch32 RVBAR
......................................................................
arch-arm: Implement AArch32 RVBAR
RVBAR has been added to the system register list since ARMv8.0-A. It is
implemented only if the highest Exception Level is different (minor)
than EL3. If that's not the case, MVBAR is used. Since the two
registers are mutually exclusive (depending on the presence of EL3),
they share the same coprocessor numbers:
p15, 0, c12, c0, 1
Rather than introducing a new register alias, we overload MVBAR so that
it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is
changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR).
N.B MVBAR is RW, whereas RVBAR is RO
Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.hh
M src/arch/arm/miscregs.cc
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 89c673e..65d2251 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -229,6 +229,11 @@
privNonSecure(v);
return *this;
}
+ chain privRead(bool v = true) const {
+ privSecureRead(v);
+ privNonSecureRead(v);
+ return *this;
+ }
chain hypRead(bool v = true) const {
info[MISCREG_HYP_RD] = v;
return *this;
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index ebe72dd..1eee781 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3165,7 +3165,10 @@
.bankedChild()
.secure().exceptUserMode();
InitReg(MISCREG_MVBAR)
- .mon().secure().exceptUserMode();
+ .mon().secure()
+ .hypRead(FullSystem && system->highestEL() == EL2)
+ .privRead(FullSystem && system->highestEL() == EL1)
+ .exceptUserMode();
InitReg(MISCREG_RMR)
.unimplemented()
.mon().secure().exceptUserMode();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13999
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Gerrit-Change-Number: 13999
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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