Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13998 )
Change subject: arch-arm: Remove SCTLR.VE bit
......................................................................
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.
Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/faults.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 1 insertion(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ab0d0de..bd06ea2 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -300,10 +300,6 @@
// ARM ARM issue C B1.8.1
bool haveSecurity = ArmSystem::haveSecurity(tc);
- // panic if SCTLR.VE because I have no idea what to do with vectored
- // interrupts
- SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
- assert(!sctlr.ve);
// Check for invalid modes
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
assert(haveSecurity || cpsr.mode != MODE_MON);
@@ -318,6 +314,7 @@
base = tc->readMiscReg(MISCREG_HVBAR);
break;
default:
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
if (sctlr.v) {
base = HighVecs;
} else {
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index 0a86236..c3ee6ca 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -319,7 +319,6 @@
// DC CVAC and IC IVAU instructions
// (AArch64 SCTLR_EL1 only)
Bitfield<25> ee; // Exception Endianness
- Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
Bitfield<24> e0e; // Endianness of explicit data accesses at
EL0
// (AArch64 SCTLR_EL1 only)
Bitfield<23> xp; // Extended page table enable (dropped in
ARMv7)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Gerrit-Change-Number: 13998
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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