Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14935
Change subject: mem-cache: Do not wait for data access on writes
......................................................................
mem-cache: Do not wait for data access on writes
When dealing with writes, the access is always done sequentially,
therefore there is no need to take the dataLatency into account,
as the fill can be done while responding. Read-Modify-Writes are
a special case that needs to wait for the read, but the fill can
still be done while responding.
Change-Id: Ifc52b7f284ec55903a4707141e425bd4272569de
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M src/mem/cache/base.cc
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index e4f2f16..bb52325 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -946,9 +946,14 @@
blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);
// Calculate access latency on top of when the packet arrives. This
- // takes into account the bus delay.
- lat = calculateAccessLatency(blk, pkt->headerDelay,
- tag_latency);
+ // takes into account the bus delay. A write can only be sequential,
+ // and the response can be created while the fill is being done. RMW
+ // is a special case that needs to do a read before the fill.
+ if (pkt->isWrite() && !pkt->isRead()) {
+ lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
+ } else {
+ lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
+ }
DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
blk ? "hit " + blk->print() : "miss");
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifc52b7f284ec55903a4707141e425bd4272569de
Gerrit-Change-Number: 14935
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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