Hello Gabe Black, Anthony Gutierrez, Nikos Nikoleris, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

    https://gem5-review.googlesource.com/c/public/gem5/+/13715

to look at the new patch set (#11).

Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
50 files changed, 1,369 insertions(+), 105 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13715
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-Reviewer: Alec Roelke <alec.roe...@gmail.com>
Gerrit-Reviewer: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-CC: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-CC: Brandon Potter <brandon.pot...@amd.com>
Gerrit-MessageType: newpatchset
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