Hello Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13515
to look at the new patch set (#12).
Change subject: arch-arm,cpu: Add initial support for Arm SVE
......................................................................
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.
Additional authors:
- Javier Setoain <javier.seto...@arm.com>
- Gabor Dozsa <gabor.do...@arm.com>
- Giacomo Travaglini <giacomo.travagl...@arm.com>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/vec_reg.hh
M src/cpu/FuncUnit.py
M src/cpu/checker/thread_context.hh
M src/cpu/exetrace.cc
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/thread_context.hh
M src/cpu/op_class.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
49 files changed, 11,209 insertions(+), 61 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 12
Gerrit-Owner: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newpatchset
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
