Ayaz Akram has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15857

Change subject: tests: add cpu tests to the new testing infrastructure
......................................................................

tests: add cpu tests to the new testing infrastructure

Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08
Signed-off-by: Ayaz Akram <yazak...@ucdavis.edu>
---
A tests/gem5/cpu_tests/benchmarks/Bubblesort.c
A tests/gem5/cpu_tests/benchmarks/FloatMM.c
A tests/gem5/cpu_tests/benchmarks/Makefile.arm
A tests/gem5/cpu_tests/benchmarks/Makefile.x86
A tests/gem5/cpu_tests/ref/Bubblesort
A tests/gem5/cpu_tests/ref/FloatMM
A tests/gem5/cpu_tests/run.py
A tests/gem5/cpu_tests/test.py
8 files changed, 647 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/cpu_tests/benchmarks/Bubblesort.c b/tests/gem5/cpu_tests/benchmarks/Bubblesort.c
new file mode 100644
index 0000000..7bd520f
--- /dev/null
+++ b/tests/gem5/cpu_tests/benchmarks/Bubblesort.c
@@ -0,0 +1,174 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#define  nil           0
+#define         false          0
+#define  true          1
+#define  bubblebase    1.61f
+#define  dnfbase       3.5f
+#define  permbase      1.75f
+#define  queensbase 1.83f
+#define  towersbase 2.39f
+#define  quickbase     1.92f
+#define  intmmbase     1.46f
+#define  treebase      2.5f
+#define  mmbase        0.0f
+#define  fpmmbase      2.92f
+#define  puzzlebase    0.5f
+#define  fftbase       0.0f
+#define  fpfftbase     4.44f
+    /* Towers */
+#define maxcells        18
+
+    /* Intmm, Mm */
+#define rowsize         40
+
+    /* Puzzle */
+#define size            511
+#define classmax        3
+#define typemax         12
+#define d                   8
+
+    /* Bubble, Quick */
+#define sortelements 5000
+#define srtelements  500
+
+    /* fft */
+#define fftsize         256
+#define fftsize2        129
+/*
+type */
+    /* Perm */
+#define permrange     10
+
+   /* tree */
+struct node {
+        struct node *left,*right;
+        int val;
+};
+
+    /* Towers */ /*
+    discsizrange = 1..maxcells; */
+#define    stackrange  3
+/*    cellcursor = 0..maxcells; */
+struct    element {
+        int discsize;
+        int next;
+};
+/*    emsgtype = packed array[1..15] of char;
+*/
+    /* Intmm, Mm */ /*
+    index = 1 .. rowsize;
+    intmatrix = array [index,index] of integer;
+    realmatrix = array [index,index] of real;
+*/
+    /* Puzzle */ /*
+    piececlass = 0..classmax;
+    piecetype = 0..typemax;
+    position = 0..size;
+*/
+    /* Bubble, Quick */ /*
+    listsize = 0..sortelements;
+    sortarray = array [listsize] of integer;
+*/
+    /* FFT */
+struct    complex { float rp, ip; } ;
+/*
+    carray = array [1..fftsize] of complex ;
+    c2array = array [1..fftsize2] of complex ;
+*/
+
+float value, fixed, floated;
+
+    /* global */
+long    seed;  /* converted to long for 16 bit WR*/
+
+    /* Perm */
+int    permarray[permrange+1];
+/* converted pctr to unsigned int for 16 bit WR*/
+unsigned int    pctr;
+
+    /* tree */
+struct node *tree;
+
+    /* Towers */
+int       stack[stackrange+1];
+struct element    cellspace[maxcells+1];
+int    freelist,  movesdone;
+
+    /* Intmm, Mm */
+
+int   ima[rowsize+1][rowsize+1], imb[rowsize+1][rowsize+1],
+      imr[rowsize+1][rowsize+1];
+float rma[rowsize+1][rowsize+1], rmb[rowsize+1][rowsize+1],
+      rmr[rowsize+1][rowsize+1];
+
+    /* Puzzle */
+int    piececount[classmax+1], class[typemax+1], piecemax[typemax+1];
+int    puzzl[size+1], p[typemax+1][size+1], n, kount;
+
+    /* Bubble, Quick */
+int sortlist[sortelements+1], biggest, littlest, top;
+
+    /* FFT */
+struct complex    z[fftsize+1], w[fftsize+1], e[fftsize2+1];
+float    zr, zi;
+
+void Initrand () {
+    seed = 74755L;   /* constant to long WR*/
+}
+
+int Rand () {
+    seed = (seed * 1309L + 13849L) & 65535L;  /* constants to long WR*/
+    return( (int)seed );     /* typecast back to int WR*/
+}
+
+
+    /* Sorts an array using bubblesort */
+
+void bInitarr()        {
+        int i;
+        long temp; /* converted temp to long for 16 bit WR*/
+        Initrand();
+        biggest = 0; littlest = 0;
+        for ( i = 1; i <= srtelements; i++ ) {
+            temp = Rand();
+            /* converted constants to long in
+             * next stmt, typecast back to int WR*/
+            sortlist[i] = (int)(temp - (temp/100000L)*100000L - 50000L);
+            if ( sortlist[i] > biggest ) biggest = sortlist[i];
+            else if ( sortlist[i] < littlest ) littlest = sortlist[i];
+        }
+}
+
+void Bubble(int run) {
+        int i, j;
+        bInitarr();
+        top=srtelements;
+
+        while ( top>1 ) {
+
+                i=1;
+                while ( i<top ) {
+
+                        if ( sortlist[i] > sortlist[i+1] ) {
+                                j = sortlist[i];
+                                sortlist[i] = sortlist[i+1];
+                                sortlist[i+1] = j;
+                        }
+                        i=i+1;
+                }
+
+                top=top-1;
+        }
+ if ( (sortlist[1] != littlest) || (sortlist[srtelements] != biggest) )
+        printf ( "Error3 in Bubble.\n");
+        printf("%d\n", sortlist[run + 1]);
+}
+
+int main()
+{
+        int i;
+        for (i = 0; i < 1; i++) Bubble(i);
+        return 0;
+}
diff --git a/tests/gem5/cpu_tests/benchmarks/FloatMM.c b/tests/gem5/cpu_tests/benchmarks/FloatMM.c
new file mode 100644
index 0000000..db05a16
--- /dev/null
+++ b/tests/gem5/cpu_tests/benchmarks/FloatMM.c
@@ -0,0 +1,164 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#define  nil           0
+#define         false          0
+#define  true          1
+#define  bubblebase    1.61f
+#define  dnfbase       3.5f
+#define  permbase      1.75f
+#define  queensbase 1.83f
+#define  towersbase 2.39f
+#define  quickbase     1.92f
+#define  intmmbase     1.46f
+#define  treebase      2.5f
+#define  mmbase        0.0f
+#define  fpmmbase      2.92f
+#define  puzzlebase    0.5f
+#define  fftbase       0.0f
+#define  fpfftbase     4.44f
+    /* Towers */
+#define maxcells        18
+
+    /* Intmm, Mm */
+#define rowsize         40
+
+    /* Puzzle */
+#define size            511
+#define classmax        3
+#define typemax         12
+#define d                   8
+
+    /* Bubble, Quick */
+#define sortelements 5000
+#define srtelements  500
+
+    /* fft */
+#define fftsize         256
+#define fftsize2        129
+/*
+type */
+    /* Perm */
+#define permrange     10
+
+   /* tree */
+struct node {
+        struct node *left,*right;
+        int val;
+};
+
+    /* Towers */ /*
+    discsizrange = 1..maxcells; */
+#define    stackrange  3
+/*    cellcursor = 0..maxcells; */
+struct    element {
+        int discsize;
+        int next;
+};
+/*    emsgtype = packed array[1..15] of char;
+*/
+    /* Intmm, Mm */ /*
+    index = 1 .. rowsize;
+    intmatrix = array [index,index] of integer;
+    realmatrix = array [index,index] of real;
+*/
+    /* Puzzle */ /*
+    piececlass = 0..classmax;
+    piecetype = 0..typemax;
+    position = 0..size;
+*/
+    /* Bubble, Quick */ /*
+    listsize = 0..sortelements;
+    sortarray = array [listsize] of integer;
+*/
+    /* FFT */
+struct    complex { float rp, ip; } ;
+/*
+    carray = array [1..fftsize] of complex ;
+    c2array = array [1..fftsize2] of complex ;
+*/
+
+float value, fixed, floated;
+
+    /* global */
+long    seed;  /* converted to long for 16 bit WR*/
+
+    /* Perm */
+int    permarray[permrange+1];
+/* converted pctr to unsigned int for 16 bit WR*/
+unsigned int    pctr;
+
+    /* tree */
+struct node *tree;
+
+    /* Towers */
+int       stack[stackrange+1];
+struct element    cellspace[maxcells+1];
+int    freelist,  movesdone;
+
+    /* Intmm, Mm */
+
+int   ima[rowsize+1][rowsize+1], imb[rowsize+1][rowsize+1],
+      imr[rowsize+1][rowsize+1];
+float rma[rowsize+1][rowsize+1], rmb[rowsize+1][rowsize+1],
+      rmr[rowsize+1][rowsize+1];
+
+    /* Puzzle */
+int    piececount[classmax+1], class[typemax+1], piecemax[typemax+1];
+int    puzzl[size+1], p[typemax+1][size+1], n, kount;
+
+    /* Bubble, Quick */
+int sortlist[sortelements+1], biggest, littlest, top;
+
+    /* FFT */
+struct complex    z[fftsize+1], w[fftsize+1], e[fftsize2+1];
+float    zr, zi;
+
+void Initrand () {
+    seed = 74755L;   /* constant to long WR*/
+}
+
+int Rand () {
+    seed = (seed * 1309L + 13849L) & 65535L;  /* constants to long WR*/
+    return( (int)seed );     /* typecast back to int WR*/
+}
+
+
+    /* Multiplies two real matrices. */
+
+void rInitmatrix ( float m[rowsize+1][rowsize+1] ) {
+        int temp, i, j;
+        for ( i = 1; i <= rowsize; i++ )
+            for ( j = 1; j <= rowsize; j++ ) {
+                temp = Rand();
+                        m[i][j] = (float)(temp -
+                                        (temp/120)*120 - 60)/3;
+        }
+}
+
+void rInnerproduct(float *result, float a[rowsize+1][rowsize+1],
+                float b[rowsize+1][rowsize+1], int row, int column) {
+        /* computes the inner product of A[row,*] and B[*,column] */
+        int i;
+        *result = 0.0f;
+ for (i = 1; i<=rowsize; i++) *result = *result+a[row][i]*b[i][column];
+}
+
+void Mm (int run)    {
+    int i, j;
+    Initrand();
+    rInitmatrix (rma);
+    rInitmatrix (rmb);
+    for ( i = 1; i <= rowsize; i++ )
+                for ( j = 1; j <= rowsize; j++ )
+                        rInnerproduct(&rmr[i][j],rma,rmb,i,j);
+    if (run < rowsize)
+      printf("%f\n", rmr[run + 1][run + 1]);
+}
+
+int main()
+{
+        int i;
+        for (i = 0; i < 1; i++) Mm(i);
+        return 0;
+}
diff --git a/tests/gem5/cpu_tests/benchmarks/Makefile.arm b/tests/gem5/cpu_tests/benchmarks/Makefile.arm
new file mode 100644
index 0000000..8fa0a30
--- /dev/null
+++ b/tests/gem5/cpu_tests/benchmarks/Makefile.arm
@@ -0,0 +1,22 @@
+SERVER_USER=jason@
+SERVER_PATH=/z/www/htdocs/dist/current/gem5/cpu_tests/benchmarks/bin/arm
+FETCH_PATH=http://gem5.org/dist/current/gem5/cpu_tests/benchmarks/bin/arm
+UPLOAD_LOCATION=$(SERVER_USER)daystrom.gem5.org:$(SERVER_PATH)
+
+all: Bubblesort FloatMM
+
+upload: Bubblesort FloatMM
+       scp Bubblesort FloatMM $(UPLOAD_LOCATION)
+
+Bubblesort: Bubblesort.c dockcross-arm64
+       ./dockcross-arm64 bash -c '$$CC Bubblesort.c -o Bubblesort -static'
+
+FloatMM: FloatMM.c dockcross-arm64
+       ./dockcross-arm64 bash -c '$$CC FloatMM.c -o FloatMM -static'
+
+dockcross-arm64:
+       docker run --rm dockcross/linux-arm64 > ./dockcross-arm64
+       chmod +x ./dockcross-arm64
+
+clean:
+       rm -f dockcross* Bubblesort FloatMM
diff --git a/tests/gem5/cpu_tests/benchmarks/Makefile.x86 b/tests/gem5/cpu_tests/benchmarks/Makefile.x86
new file mode 100644
index 0000000..2980ebc
--- /dev/null
+++ b/tests/gem5/cpu_tests/benchmarks/Makefile.x86
@@ -0,0 +1,22 @@
+SERVER_USER=jason@
+SERVER_PATH=/z/www/htdocs/dist/current/gem5/cpu_tests/benchmarks/bin/x86
+FETCH_PATH=http://gem5.org/dist/current/gem5/cpu_tests/benchmarks/bin/x86
+UPLOAD_LOCATION=$(SERVER_USER)daystrom.gem5.org:$(SERVER_PATH)
+
+all: Bubblesort FloatMM
+
+upload: Bubblesort FloatMM
+       scp Bubblesort FloatMM $(UPLOAD_LOCATION)
+
+Bubblesort: Bubblesort.c dockcross-x64
+       ./dockcross-x64 bash -c '$$CC Bubblesort.c -o Bubblesort -static'
+
+FloatMM: FloatMM.c dockcross-x64
+       ./dockcross-x64 bash -c '$$CC FloatMM.c -o FloatMM -static'
+
+dockcross-x64:
+       docker run --rm dockcross/linux-x64 > ./dockcross-x64
+       chmod +x ./dockcross-x64
+
+clean:
+       rm -f dockcross* Bubblesort FloatMM
diff --git a/tests/gem5/cpu_tests/ref/Bubblesort b/tests/gem5/cpu_tests/ref/Bubblesort
new file mode 100644
index 0000000..79d2ae3
--- /dev/null
+++ b/tests/gem5/cpu_tests/ref/Bubblesort
@@ -0,0 +1,6 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+
+Global frequency set at 1000000000000 ticks per second
+-50000
diff --git a/tests/gem5/cpu_tests/ref/FloatMM b/tests/gem5/cpu_tests/ref/FloatMM
new file mode 100644
index 0000000..6539627
--- /dev/null
+++ b/tests/gem5/cpu_tests/ref/FloatMM
@@ -0,0 +1,6 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+
+Global frequency set at 1000000000000 ticks per second
+-776.000061
diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
new file mode 100644
index 0000000..e2141e1
--- /dev/null
+++ b/tests/gem5/cpu_tests/run.py
@@ -0,0 +1,167 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2018 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import os
+import argparse
+
+import m5
+from m5.objects import *
+
+class L1Cache(Cache):
+    """Simple L1 Cache with default values"""
+
+    assoc = 8
+    tag_latency = 1
+    data_latency = 1
+    response_latency = 1
+    mshrs = 16
+    tgts_per_mshr = 20
+
+    def connectBus(self, bus):
+        """Connect this cache to a memory-side bus"""
+        self.mem_side = bus.slave
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU-side port
+           This must be defined in a subclass"""
+        raise NotImplementedError
+
+class L1ICache(L1Cache):
+    """Simple L1 instruction cache with default values"""
+
+    # Set the default size
+    size = '32kB'
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU icache port"""
+        self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+    """Simple L1 data cache with default values"""
+
+    # Set the default size
+    size = '32kB'
+
+    def connectCPU(self, cpu):
+        """Connect this cache's port to a CPU dcache port"""
+        self.cpu_side = cpu.dcache_port
+
+class L2Cache(Cache):
+    """Simple L2 Cache with default values"""
+
+    # Default parameters
+    size = '512kB'
+    assoc = 16
+    tag_latency = 10
+    data_latency = 10
+    response_latency = 1
+    mshrs = 20
+    tgts_per_mshr = 12
+
+    def connectCPUSideBus(self, bus):
+        self.cpu_side = bus.master
+
+    def connectMemSideBus(self, bus):
+        self.mem_side = bus.slave
+
+
+class MySimpleMemory(SimpleMemory):
+    latency = '1ns'
+
+valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
+             'TimingSimpleCPU': TimingSimpleCPU,
+             'MinorCPU': MinorCPU,
+             'DerivO3CPU': DerivO3CPU
+            }
+valid_mem = {'SimpleMemory': MySimpleMemory,
+             'DDR3_1600_8x8': DDR3_1600_8x8
+            }
+
+parser = argparse.ArgumentParser()
+parser.add_argument('binary', type = str)
+parser.add_argument('--cpu', choices = valid_cpu.keys(),
+                    default = 'TimingSimpleCPU')
+parser.add_argument('--mem', choices = valid_mem.keys(),
+                    default = 'SimpleMemory')
+
+args = parser.parse_args()
+
+system = System()
+
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+if args.cpu != "AtomicSimpleCPU":
+        system.mem_mode = 'timing'
+
+system.mem_ranges = [AddrRange('512MB')]
+
+system.cpu = valid_cpu[args.cpu]()
+
+if args.cpu == "AtomicSimpleCPU":
+    system.membus = SystemXBar()
+    system.cpu.icache_port = system.membus.slave
+    system.cpu.dcache_port = system.membus.slave
+else:
+    system.cpu.l1d = L1DCache()
+    system.cpu.l1i = L1ICache()
+    system.l1_to_l2 = L2XBar()
+    system.l2cache = L2Cache()
+    system.membus = SystemXBar()
+    system.cpu.l1d.connectCPU(system.cpu)
+    system.cpu.l1d.connectBus(system.l1_to_l2)
+    system.cpu.l1i.connectCPU(system.cpu)
+    system.cpu.l1i.connectBus(system.l1_to_l2)
+    system.l2cache.connectCPUSideBus(system.l1_to_l2)
+    system.l2cache.connectMemSideBus(system.membus)
+
+system.cpu.createInterruptController()
+if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+    system.cpu.interrupts[0].pio = system.membus.master
+    system.cpu.interrupts[0].int_master = system.membus.slave
+    system.cpu.interrupts[0].int_slave = system.membus.master
+
+system.mem_ctrl = valid_mem[args.mem]()
+system.mem_ctrl.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.master
+system.system_port = system.membus.slave
+
+process = Process()
+process.cmd = [args.binary]
+system.cpu.workload = process
+system.cpu.createThreads()
+
+root = Root(full_system = False, system = system)
+m5.instantiate()
+
+exit_event = m5.simulate()
+
+if exit_event.getCause() != 'exiting with last active thread context':
+    exit(1)
diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
new file mode 100644
index 0000000..5a4119a
--- /dev/null
+++ b/tests/gem5/cpu_tests/test.py
@@ -0,0 +1,86 @@
+# Copyright (c) 2018 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+'''
+Test file containing simple workloads to run on CPU models.
+Each test takes ~10 seconds to run.
+'''
+
+from testlib import *
+
+valid_isas = ('x86', 'arm')
+
+workloads = ('Bubblesort','FloatMM')
+
+for isa in valid_isas:
+    bm_dir = joinpath('gem5/cpu_tests/benchmarks/bin/', isa)
+    for workload in workloads:
+        ref_path = joinpath(getcwd(), 'ref', workload)
+        verifiers = (
+                verifier.MatchStdout(ref_path),
+        )
+
+        workload_binary = DownloadedProgram(bm_dir, workload)
+        workload_path = workload_binary.path
+
+        gem5_verify_config(
+                name='cpu_test_atomic_{}'.format(workload),
+                verifiers=verifiers,
+                config=joinpath(getcwd(), 'run.py'),
+                config_args=['--cpu=AtomicSimpleCPU', workload_path],
+                valid_isas=(isa.upper(),),
+                fixtures=[workload_binary]
+        )
+
+        gem5_verify_config(
+                name='cpu_test_timing_{}'.format(workload),
+                verifiers=verifiers,
+                config=joinpath(getcwd(), 'run.py'),
+                config_args=['--cpu=TimingSimpleCPU', workload_path],
+                valid_isas=(isa.upper(),),
+                fixtures=[workload_binary]
+        )
+
+        gem5_verify_config(
+                name='cpu_test_minor_{}'.format(workload),
+                verifiers=verifiers,
+                config=joinpath(getcwd(), 'run.py'),
+                config_args=['--cpu=MinorCPU', workload_path],
+                valid_isas=(isa.upper(),),
+                fixtures=[workload_binary]
+        )
+
+        gem5_verify_config(
+                name='cpu_test_o3_{}'.format(workload),
+                verifiers=verifiers,
+                config=joinpath(getcwd(), 'run.py'),
+                config_args=['--cpu=DerivO3CPU', workload_path],
+                valid_isas=(isa.upper(),),
+                fixtures=[workload_binary]
+        )
+

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08
Gerrit-Change-Number: 15857
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-MessageType: newchange
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