[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Initialize interrupt mask

[Tuan Ta (Gerrit)]

Tuan Ta has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/16162

Change subject: arch-riscv: Initialize interrupt mask
......................................................................

arch-riscv: Initialize interrupt mask

This patch initializes RISCV interrupt mask to 0.

Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
---
M src/arch/riscv/interrupts.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 912bf45..a847220 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -48,7 +48,7 @@
 namespace RiscvISA {

 /*
- * This is based on version 1.10 of the RISC-V privileged ISA reference,
+ * This is based on version 2.10 of the RISC-V privileged ISA reference,
  * chapter 3.1.14.
  */
 class Interrupts : public SimObject
@@ -74,7 +74,7 @@
     std::bitset<NumInterruptTypes>
     globalMask(ThreadContext *tc) const
     {
-        INTERRUPT mask;
+        INTERRUPT mask = 0;
         STATUS status = tc->readMiscReg(MISCREG_STATUS);
         if (status.mie)
             mask.mei = mask.mti = mask.msi = 1;

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Gerrit-Change-Number: 16162
Gerrit-PatchSet: 1
Gerrit-Owner: Tuan Ta <q...@cornell.edu>
Gerrit-MessageType: newchange
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