Hello Javier,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17288
to review the following change.
Change subject: arch-arm: Fix use of bitwise operators on booleans
......................................................................
arch-arm: Fix use of bitwise operators on booleans
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/insts/sve.isa
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..b1c351f 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3178,11 +3178,11 @@
sveBinInst('asrr', 'Asrr', 'SimdAluOp', unsignedTypes, asrrCode,
PredType.MERGE, True)
# BIC (vectors, predicated)
- bicCode = 'destElem = srcElem1 & ~srcElem2;'
+ bicCode = 'destElem = srcElem1 && !srcElem2;'
sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
PredType.MERGE, True)
# BIC (vectors, unpredicated)
- bicCode = 'destElem = srcElem1 & ~srcElem2;'
+ bicCode = 'destElem = srcElem1 && !srcElem2;'
sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
# BIC, BICS (predicates)
svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17288
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Gerrit-Change-Number: 17288
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Javier <javier.seto...@gmail.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
